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Merge pull request #1423 from zyp/improve_dma 

Improve DMA
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enjoy-digital 2022-09-14 09:57:43 +02:00 committed by GitHub
parent 89bb688500 3c4c12a72f
commit 0adb604c97
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1 changed files with 1 additions and 2 deletions
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litex/soc/cores/dma.py
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@ -182,13 +182,12 @@ class WishboneDMAWriter(Module, AutoCSR):
self.submodules += fsm self.submodules += fsm
self.comb += fsm.reset.eq(~self._enable.storage) self.comb += fsm.reset.eq(~self._enable.storage)
fsm.act("IDLE", fsm.act("IDLE",
self.sink.ready.eq(1),
NextValue(offset, 0), NextValue(offset, 0),
NextState("RUN"), NextState("RUN"),
) )
fsm.act("RUN", fsm.act("RUN",
self._sink.valid.eq(self.sink.valid), self._sink.valid.eq(self.sink.valid),
self._sink.last.eq(offset == (length - 1)), self._sink.last.eq(self.sink.last | (offset + 1 == length)),
self._sink.address.eq(base + offset), self._sink.address.eq(base + offset),
self._sink.data.eq(self.sink.data), self._sink.data.eq(self.sink.data),
self.sink.ready.eq(self._sink.ready), self.sink.ready.eq(self._sink.ready),