cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)

misoclib/com/liteeth/example_designs/targets/tty.py

@@ -3,7 +3,6 @@ from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.generic import *
 
 from targets.base import BaseSoC
 from misoclib.com.liteeth.frontend.tty import LiteEthTTY

misoclib/cpu/identifier.py

@@ -1,7 +1,7 @@
 from migen.fhdl.std import *
 from migen.bank.description import *
 
-from misoclib.cpu.peripherals.identifier import git
+from misoclib.cpu import git
 
 
 class Identifier(Module, AutoCSR):

misoclib/soc/__init__.py

@@ -7,7 +7,7 @@ from migen.bus import wishbone, csr, wishbone2csr
 from misoclib.com.uart.phy import UARTPHY
 from misoclib.com import uart
 from misoclib.cpu import lm32, mor1kx
-from misoclib.cpu.peripherals import identifier, timer
+from misoclib.cpu import identifier, timer
 
 
 def mem_decoder(address, start=26, end=29):

targets/mlabs_video.py

@@ -67,7 +67,7 @@ class BaseSoC(SDRAMSoC):
 INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
 INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
 """)
-        platform.add_source_dir(os.path.join("misoclib", "others", "mxcrg"))
+        platform.add_source_dir(os.path.join("misoclib", "others"))
 
 
 class MiniSoC(BaseSoC):