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Merge pull request #1470 from shenki/update-microwatt 

Update Microwatt
This commit is contained in:
Tim 'mithro' Ansell 2022-10-26 21:10:32 -07:00 committed by GitHub
parent 611b84ccee 4ccf9f487d
commit e570b612b2
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 8 additions and 8 deletions
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4
litex/build/vhd2v_converter.py
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@ -102,8 +102,8 @@ class VHD2VConverter(Module):
# platform able to synthesis verilog and vhdl -> no conversion # platform able to synthesis verilog and vhdl -> no conversion
if self._platform.support_mixed_language and not self._force_convert: if self._platform.support_mixed_language and not self._force_convert:
ip_params = self._params ip_params = self._params
for file in self._files: for file in self._sources:
platform.add_source(file) self._platform.add_source(file)
else: # platform is only able to synthesis verilog -> convert vhdl to verilog else: # platform is only able to synthesis verilog -> convert vhdl to verilog
# check if more than one core is instanciated # check if more than one core is instanciated
# if so -> append with _X # if so -> append with _X

10
litex/soc/cores/cpu/microwatt/core.py
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@ -172,12 +172,13 @@ class Microwatt(CPU):
# Instruction/Data Cache. # Instruction/Data Cache.
"cache_ram.vhdl", "cache_ram.vhdl",
"plru.vhdl", "plrufn.vhdl",
"dcache.vhdl", "dcache.vhdl",
"icache.vhdl", "icache.vhdl",
# Decode. # Decode.
"insn_helpers.vhdl", "insn_helpers.vhdl",
"predecode.vhdl",
"decode1.vhdl", "decode1.vhdl",
"control.vhdl", "control.vhdl",
"decode2.vhdl", "decode2.vhdl",
@ -219,8 +220,10 @@ class Microwatt(CPU):
from litex.build.xilinx import XilinxPlatform from litex.build.xilinx import XilinxPlatform
if isinstance(platform, XilinxPlatform) and not use_ghdl_yosys_plugin: if isinstance(platform, XilinxPlatform) and not use_ghdl_yosys_plugin:
sources.append("xilinx-mult.vhdl") sources.append("xilinx-mult.vhdl")
sources.append("xilinx-mult-32s.vhdl")
else: else:
sources.append("multiply.vhdl") sources.append("multiply.vhdl")
sources.append("multiply-32s.vhdl")
sdir = get_data_mod("cpu", "microwatt").data_location sdir = get_data_mod("cpu", "microwatt").data_location
cdir = os.path.dirname(__file__) cdir = os.path.dirname(__file__)
self.cpu_vhd2v_converter.add_sources(sdir, *sources) self.cpu_vhd2v_converter.add_sources(sdir, *sources)
@ -303,8 +306,7 @@ class XICSSlave(Module, AutoCSR):
# Add VHDL sources. # Add VHDL sources.
self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant) self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant)
@staticmethod def add_sources(self, platform, use_ghdl_yosys_plugin=False):
def add_sources(platform, use_ghdl_yosys_plugin=False):
sources = [ sources = [
# Common / Types / Helpers # Common / Types / Helpers
"decode_types.vhdl", "decode_types.vhdl",
@ -320,8 +322,6 @@ class XICSSlave(Module, AutoCSR):
cdir = os.path.dirname(__file__) cdir = os.path.dirname(__file__)
self.ics_vhd2v_converter.add_sources(sdir, *sources) self.ics_vhd2v_converter.add_sources(sdir, *sources)
self.ics_vhd2v_converter.add_source(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl")) self.ics_vhd2v_converter.add_source(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl"))
self.icp_vhd2v_converter.add_sources(sdir, *sources)
self.icp_vhd2v_converter.add_source(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl"))
def do_finalize(self): def do_finalize(self):
self.specials += Instance("xics_icp_wrapper", **self.icp_params) self.specials += Instance("xics_icp_wrapper", **self.icp_params)

2
litex_setup.py
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@ -112,7 +112,7 @@ git_repos = {
"pythondata-cpu-marocchino": GitRepo(url="https://github.com/litex-hub/"), "pythondata-cpu-marocchino": GitRepo(url="https://github.com/litex-hub/"),
# OpenPower CPU(s). # OpenPower CPU(s).
"pythondata-cpu-microwatt": GitRepo(url="https://github.com/litex-hub/", sha1=0xb940b55acff), "pythondata-cpu-microwatt": GitRepo(url="https://github.com/litex-hub/", sha1=0xb4986b23af6),
# RISC-V CPU(s). # RISC-V CPU(s).
"pythondata-cpu-blackparrot": GitRepo(url="https://github.com/litex-hub/"), "pythondata-cpu-blackparrot": GitRepo(url="https://github.com/litex-hub/"),