b1445ae743
dyld: style
2015-08-02 12:35:48 +08:00
6a1b0b342c
libdyld: handle existing but undefined symbols during lookup.
2015-08-02 05:56:11 +03:00
36e03ec8a8
libdyld: R_*_RELATIVE never specify a symbol.
2015-08-02 05:29:23 +03:00
10773db08d
libdyld: handle unaligned relocations.
2015-08-01 20:26:27 +03:00
8a0beb4cfb
unwinder: update.
2015-08-01 20:16:59 +03:00
344e1bc6de
libdyld: add support for R_OR1K_{NONE,32,GLOB_DAT}.
2015-08-01 20:16:10 +03:00
d625c43591
libbase: also pass exception PC and EA to exception handler.
2015-08-01 20:15:42 +03:00
13a50a93d9
libbase: downstream users should provide fprintf.
2015-08-01 20:14:09 +03:00
3f7f0a3151
libdyld: fix dyld_lookup algorithm.
2015-08-01 17:21:31 +03:00
d43e470e3c
libdyld: fix DT_HASH address calculation.
2015-08-01 15:49:33 +03:00
04934ff3f1
software/common.mak: use PYTHON env var
2015-07-31 18:31:04 +08:00
eb643f1132
Export _cache_init from crt0.S.
2015-07-31 02:40:52 +03:00
90314052fa
Implement a dynamic linker.
2015-07-31 02:38:38 +03:00
66839b512a
Update libunwind submodule.
2015-07-31 02:38:38 +03:00
106e4c6962
bios/sdram: fix error_cnt computation in memtest
2015-07-30 23:59:04 +02:00
94cb3cbcf6
libbase: define intptr_t.
2015-07-30 10:55:12 +03:00
4b6bd43d8e
Enable ror, ffl1 and addc for OR1K.
2015-07-30 10:55:01 +03:00
8db098dd8f
Make sure the BIOS file ends on an aligned boundary.
...
If it does not, the address to which mkmscimg.py writes the CRC
and the address from which it is read could differ.
2015-07-29 12:30:57 +03:00
a4e14f1058
Don't build base libraries and BIOS with -fPIC after all.
2015-07-29 12:09:05 +03:00
b7aff65ca9
mor1kx: enable ADDC, CMOV and FFL1 instructions
2015-07-29 00:08:21 +08:00
f2eff4d10e
soc: increase default BIOS size
2015-07-28 22:36:42 +08:00
5e6178598c
Merge branch 'master' of https://github.com/m-labs/misoc
2015-07-28 11:59:48 +02:00
405efc5560
update lm32 with "Switch to -fPIC" changes.
2015-07-28 11:11:11 +02:00
03ebc736b2
Pass -integrated-as to clang.
...
This avoids misdetection of target assembler by clang.
2015-07-28 11:51:28 +03:00
50cf70140b
Update libbase/linker-sdram.ld with -fPIC support.
2015-07-26 16:15:02 +03:00
c8ffd0c9ee
Switch to -fPIC.
...
Using -fPIC for everything allows to link the MiSoC static libraries
both into static images such as the BIOS as well as
into shared libraries.
2015-07-26 16:06:48 +03:00
a8cd3b9adc
Remove useless includes pulled in by libunwind.
...
These aren't used by libunwind in any configuration and
should be also removed in upstream.
2015-07-26 13:12:23 +03:00
f6639c1833
Add libunwind.
2015-07-26 12:59:18 +03:00
24463a168a
Add a stub getenv() implementation.
...
This is not strictly necessary to build libunwind (it can
be built with -DNDEBUG), but it will be handy while it is
debugged.
It can be removed afterwards.
2015-07-26 12:55:52 +03:00
b2710e437c
Add a stub pthread header.
...
The header implements only the pthread rwlock interface, which
never actually locks.
This is necessary to build libunwind.
2015-07-26 12:54:40 +03:00
b5048f6cf1
Add headers for the dynamic linker interface.
...
These are required for libunwind to discover
the exception frame headers.
2015-07-26 12:53:18 +03:00
7a9975ab5a
Add a stub C++ standard library.
...
This is necessary to build libunwind.
2015-07-26 12:49:21 +03:00
5502cec3da
Add basic inttypes.h.
...
This is taken from glibc. Only PRI* definitions are imported;
functions are not.
2015-07-26 12:44:13 +03:00
eef1aa77ef
Mark abort() as __attribute__((noreturn)).
2015-07-26 12:43:22 +03:00
10f719a830
Add support for fprintf(stderr, ...).
2015-07-26 12:42:53 +03:00
f5cc6fb72d
Don't use clang for anything except or1k.
2015-07-26 10:00:58 +03:00
d03dabb460
common.mak: Pass -fexceptions to clang and clang++.
...
This results in generation of .eh_frame sections. These sections
can be discarded during final linking, or included if exception
handling is desired. For exception handling to work, all sources
must be built with -fexceptions.
2015-07-26 03:30:21 +03:00
69c2a705bf
common.mak: use clang/clang++ to compile C/C++ sources.
...
Note that -integrated-as is not active by default on OR1K,
so we're still shelling out to binutils to assemble.
It is not yet possible to build everything using -integrated-as.
2015-07-26 03:28:37 +03:00
0f47876d2e
common.mak: remove RANLIB.
...
`ranlib` is not necessary on any system we can possibly build for,
as it is superseded by `ar s` for the last ten years or so (at least).
Thus, change ar invocations to `ar crs`, also removing a `l` flag
that is ignored by binutils.
2015-07-26 03:20:23 +03:00
f500b906e6
common.mak: remove AS.
...
$(AS) was never used: $(assemble) invokes the C compiler instead.
In case of LLVM, this will allow us to consistently use the LLVM
internal assembler for both inline assembly in C and assembly
sources; so, avoid ever invoking binutils as explicitly.
2015-07-26 02:46:03 +03:00
8d1c555e36
misoclib/com/uart: remove irq condition parameters and use "non-full" for tx irq, "non-empty" for rx irq.
...
An optimal solution for both sync and async mode is not easy to implement, it would requires moving CDC out of UART module and handling in the PHY with AsyncFIFO or minimal depth.
For now use the solution that works for both cases. We'll try to optimize that if we have performance issues.
2015-07-25 00:25:09 +02:00
ce11b30140
misoclib: integrate mxcrg.py in mlabs_video target, remove others directory
...
we should also get rid of mxcrg.v (similar to what is done on papilio or pipstrello)
2015-07-24 23:16:45 +02:00
b75b93df43
misoclib/com/uart: replace revered Migen FIFO function with specific _get_uart_fifo function for our use case.
2015-07-24 14:05:54 +02:00
0a115f609e
litepcie/frontend/dma: group loop index and count in loop_status register (avoid 2 register reads)
2015-07-24 13:52:57 +02:00
d73d75007e
misoclib/com/uart: cleanup and add irq condition parameters
...
- reintroduce RX/TX split (ease comprehension)
- use FIFO wrapper function from Migen.
- add tx_irq_condition and rx_irq_condition
2015-07-24 12:57:42 +02:00
b1ea3340f3
litepcie/frontend/dma: add loop counter (useful to detect missed interrupts)
2015-07-22 22:55:11 +02:00
dfc207aacb
litepcie: use data instead of dat in dma_layout (allow use of migen.actorlib.packet modules on dma dataflow)
2015-07-22 21:44:53 +02:00
40740d3ddc
litepcie: use optional platform.misoc_path to add litepcie phy wrapper verilog files
...
We should eventually try to use python package_data or data_file for that.
2015-07-22 18:09:04 +02:00
84514cf8d5
uart: remove option to refill HW from uart_write
2015-07-19 23:41:38 +02:00
a501d7c52d
uart: support async phys
2015-07-19 23:37:00 +02:00
Sebastien Bourdeauducq
whitequark
Florent Kermarrec
Robert Jordens