2e48ab568b
soc/cores/spi: make dynamic clk divider optional (can be enabled with add_clk_divider method) and only use it in add_spi_sdcard.
2020-03-27 18:44:48 +01:00
86eec1a413
Merge pull request #439 from antmicro/fix-compiler-rt
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Update removed llvm compiler-rt repo
2020-03-26 15:36:39 +01:00
5fa2cc6624
Update removed llvm compiler-rt repo
2020-03-26 10:56:28 +01:00
4abb3715d9
targets/add_constant: avoid specifying value when value is None (=default).
2020-03-26 09:45:19 +01:00
73b4347587
software/libbase/spisdcard: add USE_SPISDCARD_RECLOCKING define to easily disable reclocking.
2020-03-26 07:46:32 +01:00
b509df8bb6
integration/soc/add_uart: add USB CDC support (with ValentyUSB core).
2020-03-25 19:07:06 +01:00
76872a7afb
tools/litex_sim: simplify using uart_name=sim.
2020-03-25 19:06:37 +01:00
09a3ce0ee5
integration/soc/add_uart: add Model/Sim.
2020-03-25 18:56:58 +01:00
3f43c6a223
integration/soc/add_uart: cleanup.
2020-03-25 18:54:29 +01:00
5bcf730c77
build/tools: add replace_in_file function.
2020-03-25 16:36:53 +01:00
ffe83ef0f3
tools/litex_term: use 64 bytes as default payload_lengh (work for all confniguration) and add small delay between frames for FT245 FIFO.
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The delay still need to be investigated.
2020-03-25 09:31:51 +01:00
8f2e36927d
bios/boot: update comments.
2020-03-25 09:21:28 +01:00
1746b57a1b
Merge pull request #437 from feliks-montez/bugfix/fix-serialboot-frames
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flush rx buffer when bad crc and fix frame payload length
2020-03-25 09:18:31 +01:00
c154d8d2fc
test/test_targets: remove versa_ecp3.
2020-03-25 08:47:43 +01:00
8d999081e3
boards/targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support.
2020-03-24 20:04:18 +01:00
3eb08c7dd8
boards/platforms: remove versa_ecp3 (ECP3 no longer supported).
2020-03-24 20:02:57 +01:00
eb64169521
build/lattice/diamond: remove ECP3 support. (ECP3 is not used and no longer interesting now that ECP5 has an open-source toolchain).
2020-03-24 19:36:57 +01:00
bba5f1828b
cores/clock/ECP5PLL: add phase support.
2020-03-24 19:09:05 +01:00
0123ccc893
build/lattice/common: change LatticeECPXDDROutputImpl from ECP3 to ECP5.
2020-03-24 19:08:38 +01:00
5a402264d0
Fix off-by-one error on almost full condition for prefetch
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This causes a DRC error on the Xilinx tools when the prefetch
lines setting is 1. Don't know why this wasn't caught earlier,
but it just popped up in CI.
2020-03-24 08:04:35 +01:00
ebdc38fc91
flush rx buffer when bad crc and fix frame payload length
2020-03-23 23:04:36 -04:00
d62ef38c4b
soc/doc/csr: allow CSRField.reset to be a Migen Constant.
2020-03-23 18:47:41 +01:00
4adac90d88
cpu/vexriscv/mem_map_linux: move main_ram to allow up to 1GB.
2020-03-23 15:35:33 +01:00
63ab2ba40c
software/bios/boot/linux: move emulator.bin to main_ram and allow defining custom ram offsets.
2020-03-23 15:06:32 +01:00
d998475498
targets: remove Etherbone imports.
2020-03-21 21:39:34 +01:00
3b04efbcae
targets: switch to add_etherbone method.
2020-03-21 19:55:00 +01:00
5ad7a3b7df
integration/soc: add add_etherbone method.
2020-03-21 19:54:36 +01:00
d6b0819e4c
integration/soc/add_ethernet: add name parameter (defaults to ethmac).
2020-03-21 19:36:31 +01:00
930679efd7
targets: always use sys_clk_freq on SDRAM modules.
2020-03-21 19:36:06 +01:00
ae6ef923af
targets: fix typos in previous changes.
2020-03-21 18:26:58 +01:00
c547b2cc29
Merge pull request #436 from rob-ng15/master
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Reclock spi sdcard access after initialisation
2020-03-21 09:26:25 +01:00
011773af8d
Merge pull request #435 from enjoy-digital/spi_master_clk_divider
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soc/core/spi: add Clk Divider CSR (defaults to sys_clk_freq/spi_clk_f…
2020-03-21 09:25:37 +01:00
2bf31a31da
Reclock spi sdcard access after initialisation
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Depends upon https://github.com/enjoy-digital/litex/pull/435
After initialising the card, reclock the card, aiming for ~16MHz (divider is rounded up, as slower speed is safer), but a maximum of half of the processor speed.
Tested with the card being clocked to 12.5MHz on de10nano
2020-03-21 07:37:21 +00:00
f03d862c06
targets: switch to add_ethernet method instead of EthernetSoC.
2020-03-20 23:46:15 +01:00
4e9a8ffe9c
targets: switch to SoCCore/add_sdram instead of SoCSDRAM.
2020-03-20 22:02:36 +01:00
61c9e54a90
soc/core/spi: add Clk Divider CSR (defaults to sys_clk_freq/spi_clk_freq).
2020-03-20 19:49:42 +01:00
dd7718b4fe
targets/arty: use new ISERDESE2 MEMORY mode.
2020-03-20 18:58:31 +01:00
fca52d110d
Merge branch 'master' of http://github.com/enjoy-digital/litex
2020-03-20 18:54:51 +01:00
0f35664839
Merge pull request #434 from rob-ng15/master
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Use <stdint.h> to provide structure sizes
2020-03-20 18:05:21 +01:00
f3c233776e
Use <stdint.h> to provide structure sizes
2020-03-20 11:35:05 +00:00
c2ebbcbf6c
Use <stdint.h> for structure sizes
2020-03-20 11:34:24 +00:00
ccf7363932
integration/soc: add add_spi_flash method to add SPI Flash support to the SoC.
2020-03-20 10:24:31 +01:00
ec3e068669
targets/nexys4ddr: use LiteXSoC's add_spi_sdcard method.
2020-03-20 09:58:09 +01:00
d276036f24
integration/soc: add add_spi_sdcard method to add SPI mode SDCard support to the SoC.
2020-03-20 09:57:37 +01:00
6044570928
Merge pull request #433 from gsomlo/gls-rocket-spisdcard
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Support SPI-mode SDCard booting on Litex+Rocket (64bit) configuration
2020-03-20 09:41:56 +01:00
b960d7c574
targets/nexys4ddr: add '--with-spi-sdcard' build option
2020-03-19 21:51:44 -04:00
7a7b8905b7
platforms/nexys4ddr: add spisdcard pins.
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Synchronize with litex-boards commit #57bcadb.
2020-03-19 21:51:44 -04:00
af4de03fad
targets/nexys4ddr: make sdcard reset conditional
2020-03-19 21:51:44 -04:00
a33916bc6b
software/libbase/spisdcard: fix 4-byte FAT fields on 64-bit CPUs
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On 64-bit architectures (e.g., Rocket), 'unsigned long' means
eight (not four) bytes. Use 'unsigned int' wherever a FAT data
structure requires a four-byte field!
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-19 21:51:44 -04:00
fbadfa1764
Merge pull request #432 from esden/csr-doc-fix-int
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Don't let python convert lane number to float.
2020-03-20 09:20:02 +08:00
Florent Kermarrec
Kamil Rakoczy
bunnie
Feliks
rob-ng15
Gabriel Somlo
Sean Cross