Sebastien Bourdeauducq
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11cbdf0d4f
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build.py: support single DVI sampler
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2013-05-05 20:56:58 +02:00 |
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Sebastien Bourdeauducq
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53e5c4f59c
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build: only add UCF constraints for the cores that are present
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2013-05-02 23:56:09 +02:00 |
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Sebastien Bourdeauducq
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de76faf757
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Tell the Xilinx crapware that DCM_CLKGEN does not phase align, as some (but not all) of the ISE tools remark.
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2013-04-25 20:18:45 +02:00 |
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Sebastien Bourdeauducq
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4ff1175dcf
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Use the Migen asynchronous FIFO
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2013-04-25 19:43:26 +02:00 |
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Sebastien Bourdeauducq
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1e860c7472
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Use new Mibuild generic_platform API
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2013-03-26 17:57:17 +01:00 |
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Sebastien Bourdeauducq
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fdf7f10f54
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Automatically build CSR access functions
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2013-03-25 14:42:48 +01:00 |
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Sebastien Bourdeauducq
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0a14c3714b
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dvisampler: software controlled phase detector
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2013-03-21 00:46:29 +01:00 |
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Sebastien Bourdeauducq
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9f02ced39e
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dvisampler: add clocking and phase detector
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2013-03-17 14:43:10 +01:00 |
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Sebastien Bourdeauducq
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b2173bba9f
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Use new ClockDomain API
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2013-03-15 19:17:05 +01:00 |
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Sebastien Bourdeauducq
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eaef3464e9
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Instantiate DVI sampler core for both ports
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2013-03-13 19:56:56 +01:00 |
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Sebastien Bourdeauducq
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1e7783a41e
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build.py: use implicit get_fragment
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2013-03-12 16:13:20 +01:00 |
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Sebastien Bourdeauducq
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b854f1ad32
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build: support optional MMU
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2013-02-24 16:28:59 +01:00 |
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Sebastien Bourdeauducq
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43343b131f
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lm32: use submodule
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2013-02-24 15:57:19 +01:00 |
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Sebastien Bourdeauducq
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5649e88a90
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Use Mibuild
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2013-02-11 18:23:06 +01:00 |
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Sebastien Bourdeauducq
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4e18e45686
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Add Ethernet MAC
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2012-05-20 00:30:03 +02:00 |
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Sebastien Bourdeauducq
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48ddbf0c85
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Add build Makefile and JTAG load script
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2012-02-17 18:09:48 +01:00 |
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Sebastien Bourdeauducq
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5d1dad583b
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Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
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2012-02-17 11:04:44 +01:00 |
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Sebastien Bourdeauducq
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72f9af9d90
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Generate all clocks for the DDR PHY
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2012-02-16 18:02:37 +01:00 |
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Sebastien Bourdeauducq
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aef2e4b5e8
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Use double quotes for all strings
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2012-02-14 13:15:00 +01:00 |
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Sebastien Bourdeauducq
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b60abfaa4a
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Convert -> convert
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2012-01-05 19:27:45 +01:00 |
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Sebastien Bourdeauducq
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6664af73d1
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uart: new design using FHDL and bank (TX only, incomplete)
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2011-12-18 00:29:37 +01:00 |
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Sebastien Bourdeauducq
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411e1af980
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Proper reset generation
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2011-12-16 22:25:26 +01:00 |
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Sebastien Bourdeauducq
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ca68097ef6
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Pay a bit more attention to PEP8
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2011-12-16 16:02:49 +01:00 |
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Sebastien Bourdeauducq
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b487e99bcf
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Initial import
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2011-12-13 17:33:12 +01:00 |