Florent Kermarrec
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144ee7ea9f
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soc: fix register_rom
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2015-02-28 23:51:51 +01:00 |
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Florent Kermarrec
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5c43d4d091
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litescope: create example design derived from SoC that can be used on all targets
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2015-02-28 22:19:24 +01:00 |
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Florent Kermarrec
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165a5b6760
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soc: use self.cpu_reset_address as rom mem_map address and increase default bios size to 0xa000
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2015-02-28 20:04:51 +01:00 |
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Florent Kermarrec
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6107b7844a
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test implementation on all targets and fix issues
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2015-02-28 12:04:51 +01:00 |
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Florent Kermarrec
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8564b7eb6a
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soc: move SDRAMSoC to a separate sdram.py file (ideally part of SDRAMSoC should move mem/sdram)
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2015-02-28 11:44:14 +01:00 |
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Florent Kermarrec
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69e869893d
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remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
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2015-02-28 11:36:15 +01:00 |