5 commits

Author	SHA1	Message	Date
Florent Kermarrec	200791c81d	uart: generate ack for rx (serialboot OK with sim)	2015-03-04 00:57:37 +01:00
Florent Kermarrec	f58394f6af	soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)	2015-03-01 18:25:47 +01:00
Florent Kermarrec	096e95cb59	uart: use data instead of d on endpoint's layouts (coherency with others cores)	2015-03-01 16:56:48 +01:00
Florent Kermarrec	bd4d3cd73b	uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)	2015-03-01 12:14:34 +01:00
Florent Kermarrec	2c51adcd68	misoclib: better organization (create cores categories: cpu, mem, com, ...)	2015-02-28 09:40:44 +01:00

Renamed from misoclib/uart/__init__.py (Browse further)