Sebastien Bourdeauducq
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026457a98c
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Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately.
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2012-02-18 18:12:14 +01:00 |
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Sebastien Bourdeauducq
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5bc840b9c1
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DFI injector (untested)
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2012-02-17 23:50:10 +01:00 |
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Sebastien Bourdeauducq
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c387ce7ce5
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Map DDR PHY controls in CSR
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2012-02-17 17:34:59 +01:00 |
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Sebastien Bourdeauducq
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5d1dad583b
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Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
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2012-02-17 11:04:44 +01:00 |
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Sebastien Bourdeauducq
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72f9af9d90
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Generate all clocks for the DDR PHY
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2012-02-16 18:02:37 +01:00 |
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Sebastien Bourdeauducq
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5165ff7ec3
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Include Wishbone to ASMI bridge
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2012-02-13 23:12:57 +01:00 |
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Sebastien Bourdeauducq
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58f4f78d2c
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sram: fix sub-word write
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2012-02-06 23:13:35 +01:00 |
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Sebastien Bourdeauducq
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33f1c456bf
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top: connect UART IRQ
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2012-02-06 17:45:40 +01:00 |
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Sebastien Bourdeauducq
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9b9a510525
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Memory map
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2012-02-05 19:54:08 +01:00 |
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Sebastien Bourdeauducq
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28f00c3a9a
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Add on-chip SRAM
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2012-01-27 22:09:03 +01:00 |
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Sebastien Bourdeauducq
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6fde54c5aa
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Use meaningful class names
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2012-01-21 12:25:22 +01:00 |
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Sebastien Bourdeauducq
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f6aa95a4d0
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Use new verilog.convert API
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2012-01-20 23:00:11 +01:00 |
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Sebastien Bourdeauducq
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570ea8ccf8
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convtools -> tools
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2012-01-13 17:07:46 +01:00 |
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Sebastien Bourdeauducq
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b60abfaa4a
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Convert -> convert
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2012-01-05 19:27:45 +01:00 |
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Sebastien Bourdeauducq
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6664af73d1
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uart: new design using FHDL and bank (TX only, incomplete)
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2011-12-18 00:29:37 +01:00 |
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Sebastien Bourdeauducq
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0e30d67fa3
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Multiply system clock
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2011-12-17 15:00:18 +01:00 |
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Sebastien Bourdeauducq
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411e1af980
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Proper reset generation
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2011-12-16 22:25:26 +01:00 |
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Sebastien Bourdeauducq
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ca68097ef6
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Pay a bit more attention to PEP8
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2011-12-16 16:02:49 +01:00 |
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Sebastien Bourdeauducq
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b487e99bcf
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Initial import
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2011-12-13 17:33:12 +01:00 |