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657 Commits 40 Branches 14 Tags 51 MiB
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657 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 20528c622a mor1kx: sync 2014-10-10 15:38:05 +08:00
Sebastien Bourdeauducq e53fb88b85 uart: minor cleanup and fix 2014-10-10 15:33:27 +08:00
Florent Kermarrec 5e5f436aa6 uart: split it and use dataflow 
This make the code easier to understand and allow the reuse of UARTRX & UARTTX
on designs without CPU (e.g miscope).
 2014-10-10 15:24:47 +08:00
Florent Kermarrec c1fc0b9c97 update README with new Kintex-7 support 2014-09-26 10:36:29 +08:00
Florent Kermarrec 13fb9282db targets: add simple design (vendor agnostic and usable on all platforms with UART pins). 
Designing a SoC with Migen is easy, but we have to provide a very simple design that can
be used on all boards with only 1 clock and 2 UARTs pins defined. This will encourage the
newcomer to invest time in Migen/MiSoC and see its real potential.
 2014-09-26 10:35:15 +08:00
Sebastien Bourdeauducq 410f250d2a software: remove setjmp 2014-09-23 21:57:05 +08:00
Sebastien Bourdeauducq 14d53526be libbase: use __builtin_setjmp and __builtin_longjmp 2014-09-21 17:43:17 +08:00
Sebastien Bourdeauducq 503a2f00b5 mor1kx: sync 2014-09-12 16:00:32 +08:00
Florent Kermarrec c0c17030fd spi_flash: simplify usage by removing cmd, cmd_width, addr_width parameters 2014-09-04 15:23:39 +08:00
Sebastien Bourdeauducq 36434b62f0 sdram: merge DFII_PIX_RDDATA_SIZE and DFII_PIX_WRDATA_SIZE 2014-09-03 15:02:38 +08:00
Sebastien Bourdeauducq 2388bfabc3 bios: support DDR3 write leveling and read calibration. This makes the full DDR3 SODIMM work on the KC705. 2014-09-03 14:25:26 +08:00
Sebastien Bourdeauducq a7b4550e59 sdramphy/initsequence: cleanup and expose DDR3 MR1 value 2014-09-03 14:21:30 +08:00
Florent Kermarrec 114890ee80 sdramphy/initsequence: clean up mr1/mr2 computation on DDR3 and enable Dynamic ODT 2014-09-02 10:54:29 +08:00
Sebastien Bourdeauducq 2234f50223 k7ddrphy: add bitslip control for incoming DQ 2014-09-01 19:54:39 +08:00
Sebastien Bourdeauducq 0eeb0ad9eb targets/kc705: add ddrphy to CSR map 2014-09-01 16:40:10 +08:00
Sebastien Bourdeauducq 6decb357f1 bios: add sdrrderr 2014-09-01 15:23:37 +08:00
Sebastien Bourdeauducq 57335bdf3f bios: add DQ filtering to sdrrd, add sdrrdbuf command 2014-09-01 14:58:58 +08:00
Sebastien Bourdeauducq 5483b37c8f k7ddrphy: write leveling and read calibration support 2014-08-31 21:54:28 +08:00
Sebastien Bourdeauducq 19abe2b888 k7ddrphy: do not register T at SERDES (fixes timing problem) 2014-08-31 21:53:35 +08:00
Sebastien Bourdeauducq a2096ff083 libcompiler-rt: add moddi3 2014-08-28 16:54:12 +08:00
Sebastien Bourdeauducq 541e5abbc7 k7ddrphy: update comment 2014-08-22 19:02:57 +08:00
Sebastien Bourdeauducq 66fe45ba96 k7ddrphy: decrease CAS latency to account for cmd/data flight time 2014-08-22 18:46:01 +08:00
Sebastien Bourdeauducq b94647ab16 k7ddrphy: suppress idiotic bitgen warning about ISERDES IOBDELAY parameter 2014-08-22 18:45:25 +08:00
Sebastien Bourdeauducq 35327a427f targets/kc705: BIOS XIP 2014-08-22 17:13:10 +08:00
Sebastien Bourdeauducq 6b35c7b8ea targets/ppro: reduce SPI flash clock frequency 2014-08-22 15:24:14 +08:00
Sebastien Bourdeauducq 7b10f1821f targets/ppro: fix BIOS address 2014-08-22 15:24:00 +08:00
Florent Kermarrec 3eabec28cd make.py: add set_flash_proxy_dir to flash-bios 2014-08-22 15:04:50 +08:00
Sebastien Bourdeauducq 2f2a57dd34 targets/ppro: clean up indentation 2014-08-22 14:41:28 +08:00
Florent Kermarrec 1c381acc6f k7ddrphy: fix read_latency (CL is 2 sys_clk since we use quarter rate) 2014-08-14 22:46:06 +08:00
Florent Kermarrec acbba37f5f k7ddrphy: set bitslip to 0 on ISERDESE2 (needed at least for sim) 2014-08-14 22:46:06 +08:00
Florent Kermarrec 2e4bfe154f k7ddrphy: add ODELAYE2 on dm path to match dq path (ODELAYE2 even configure with a delay of 0 generates a delay) 2014-08-14 22:46:06 +08:00
Florent Kermarrec bb85f29f91 k7ddrphy: fix write_latency and take care of OSERDESE2 latency on oe 2014-08-14 22:46:06 +08:00
Florent Kermarrec 85b29c883a sdramphy/initsequence: fix and add format_mr0 function 2014-08-14 14:17:54 +08:00
Florent Kermarrec 9844c25df9 k7ddrphy: add SERDES reset 2014-08-14 14:16:41 +08:00
Florent Kermarrec 194a5a0491 lasmicon: fix reset_n level 2014-08-14 14:15:48 +08:00
Sebastien Bourdeauducq 3a960e9e6a flash_extra: use new programmer 2014-08-09 14:39:38 +08:00
Sebastien Bourdeauducq a6c55d8dde make.py: do not use prog.needs_flash_proxy 2014-08-09 14:38:56 +08:00
Sebastien Bourdeauducq 4d2623a87e mor1kx: sync 2014-08-09 14:32:57 +08:00
Sebastien Bourdeauducq c8dd4d2b40 k7ddrphy: send rddata_valid on all phases 2014-08-09 11:00:13 +08:00
Sebastien Bourdeauducq 41c8c172b5 targets/kc705: integrate DDR3 2014-08-08 21:58:41 +08:00
Sebastien Bourdeauducq 0ebdf2be6d bios/sdram: cleanup 2014-08-08 21:57:58 +08:00
Sebastien Bourdeauducq b61dced909 bios/sdram: set ODT and RESET_N through DFII 2014-08-08 21:57:42 +08:00
Sebastien Bourdeauducq 8deadc5760 dfii: drive ODT and RESET_N 2014-08-08 21:56:35 +08:00
Sebastien Bourdeauducq 1322c0484b lasmicon: drive ODT and RESET_N 2014-08-08 21:55:34 +08:00
Sebastien Bourdeauducq 0550cbb3ce lasmicon: add CWL to PHY settings 2014-08-08 21:55:12 +08:00
Sebastien Bourdeauducq 777ebb7875 sdramphy/gensdrphy: fix rddata_en generation 2014-08-08 21:41:07 +08:00
Sebastien Bourdeauducq a2c7ff4c0c sdramphy: initial K7 DDR3 support 2014-08-08 21:28:26 +08:00
Florent Kermarrec 293ac09673 sdramphy/bios: make sdrrd/sdrwr generic 2014-08-08 19:25:10 +08:00
Sebastien Bourdeauducq cfc37a3fa5 sdramphy/initsequence: rewrite DDR3 initialization sequence 2014-08-08 19:15:05 +08:00
Sebastien Bourdeauducq e8db842538 s6ddrphy: fix DFI interface data width computation 2014-08-08 19:14:15 +08:00