Sebastien Bourdeauducq
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a7b4550e59
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sdramphy/initsequence: cleanup and expose DDR3 MR1 value
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2014-09-03 14:21:30 +08:00 |
Florent Kermarrec
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114890ee80
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sdramphy/initsequence: clean up mr1/mr2 computation on DDR3 and enable Dynamic ODT
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2014-09-02 10:54:29 +08:00 |
|
Sebastien Bourdeauducq
|
2234f50223
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k7ddrphy: add bitslip control for incoming DQ
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2014-09-01 19:54:39 +08:00 |
|
Sebastien Bourdeauducq
|
5483b37c8f
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k7ddrphy: write leveling and read calibration support
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2014-08-31 21:54:28 +08:00 |
|
Sebastien Bourdeauducq
|
19abe2b888
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k7ddrphy: do not register T at SERDES (fixes timing problem)
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2014-08-31 21:53:35 +08:00 |
|
Sebastien Bourdeauducq
|
541e5abbc7
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k7ddrphy: update comment
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2014-08-22 19:02:57 +08:00 |
|
Sebastien Bourdeauducq
|
66fe45ba96
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k7ddrphy: decrease CAS latency to account for cmd/data flight time
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2014-08-22 18:46:01 +08:00 |
|
Sebastien Bourdeauducq
|
b94647ab16
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k7ddrphy: suppress idiotic bitgen warning about ISERDES IOBDELAY parameter
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2014-08-22 18:45:25 +08:00 |
|
Florent Kermarrec
|
1c381acc6f
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k7ddrphy: fix read_latency (CL is 2 sys_clk since we use quarter rate)
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2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
acbba37f5f
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k7ddrphy: set bitslip to 0 on ISERDESE2 (needed at least for sim)
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2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
2e4bfe154f
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k7ddrphy: add ODELAYE2 on dm path to match dq path (ODELAYE2 even configure with a delay of 0 generates a delay)
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2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
bb85f29f91
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k7ddrphy: fix write_latency and take care of OSERDESE2 latency on oe
|
2014-08-14 22:46:06 +08:00 |
|
Florent Kermarrec
|
85b29c883a
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sdramphy/initsequence: fix and add format_mr0 function
|
2014-08-14 14:17:54 +08:00 |
|
Florent Kermarrec
|
9844c25df9
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k7ddrphy: add SERDES reset
|
2014-08-14 14:16:41 +08:00 |
|
Sebastien Bourdeauducq
|
c8dd4d2b40
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k7ddrphy: send rddata_valid on all phases
|
2014-08-09 11:00:13 +08:00 |
|
Sebastien Bourdeauducq
|
777ebb7875
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sdramphy/gensdrphy: fix rddata_en generation
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2014-08-08 21:41:07 +08:00 |
|
Sebastien Bourdeauducq
|
a2c7ff4c0c
|
sdramphy: initial K7 DDR3 support
|
2014-08-08 21:28:26 +08:00 |
|
Florent Kermarrec
|
293ac09673
|
sdramphy/bios: make sdrrd/sdrwr generic
|
2014-08-08 19:25:10 +08:00 |
|
Sebastien Bourdeauducq
|
cfc37a3fa5
|
sdramphy/initsequence: rewrite DDR3 initialization sequence
|
2014-08-08 19:15:05 +08:00 |
|
Sebastien Bourdeauducq
|
e8db842538
|
s6ddrphy: fix DFI interface data width computation
|
2014-08-08 19:14:15 +08:00 |
|
Florent Kermarrec
|
25b3aff6f1
|
sdramphy: add init sequence for DDR3
|
2014-07-31 10:29:32 +08:00 |
|
Florent Kermarrec
|
f4c0648289
|
gensdrphy: fix dm generation
|
2014-05-21 21:16:06 +02:00 |
|
Florent Kermarrec
|
54339a6d5b
|
gensdrphy: fix memtype and change phase shift in comments.
|
2014-05-16 16:52:24 +02:00 |
|
Sebastien Bourdeauducq
|
6298624f98
|
sdramphy: remove fixed parameters
|
2014-05-14 16:08:40 +02:00 |
|
Florent Kermarrec
|
774464155a
|
gensdrphy: clean up and implement data mask
|
2014-05-01 16:17:50 +02:00 |
Robert Jordens
|
3ab9f234d0
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gensdrphy: use 'dm' not 'dqm' (follow s6ddrphy and majority of platforms)
|
2014-04-25 10:38:57 +02:00 |
|
Florent Kermarrec
|
1adceb8276
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sdramphy: move and clean up s6ddrphy, add generic SDRAM PHY
|
2014-04-17 19:38:25 +02:00 |