Florent Kermarrec
f67b39739e
soc/integration/add_ethernet: Expose full_memory_we parameter.
2024-09-05 10:18:12 +02:00
Dolu1990
1f2418de3b
core/usb_ohci: fix SDRTristate clock
2024-09-05 10:17:22 +02:00
Dolu1990
84e7e816c7
efinix: pll now force the generated clock into cd.clk *WARNING*
2024-09-05 10:16:43 +02:00
Andrew Dennison
d3161ad74c
build/efinix/platform: fix get_pin_name()
...
get_pin_name did not include the resource index, so additional core
instances were generated with identical pin names. See below for
examples.
Also only adds slice index for slices with more than one io for cleaner
naming.
("i2c", 0,
Subsignal("scl", Pins(...)),
Subsignal("sda", Pins(...)),
),
("i2c", 1,
Subsignal("scl", Pins(...)),
Subsignal("sda", Pins(...)),
),
Before:
output wire i2c0_oe,
input wire i2c0_scl,
input wire i2c0_sda,
input wire i2c1_scl,
input wire i2c1_sda,
input wire i2c_scl0_IN,
input wire i2c_scl0_IN_1,
input wire i2c_scl0_IN_2,
output wire i2c_scl0_OE,
output wire i2c_scl0_OE_1,
output wire i2c_scl0_OE_2,
input wire i2c_sda0_IN,
input wire i2c_sda0_IN_1,
input wire i2c_sda0_IN_2,
output wire i2c_sda0_OE,
output wire i2c_sda0_OE_1,
output wire i2c_sda0_OE_2,
After:
output wire i2c0_oe,
input wire i2c0_scl,
input wire i2c0_scl_IN,
output wire i2c0_scl_OE,
output wire i2c0_scl_OUT,
input wire i2c0_sda,
input wire i2c0_sda_IN,
output wire i2c0_sda_OE,
output wire i2c0_sda_OUT,
input wire i2c1_scl,
input wire i2c1_scl_IN,
output wire i2c1_scl_OE,
output wire i2c1_scl_OUT,
input wire i2c1_sda,
input wire i2c1_sda_IN,
output wire i2c1_sda_OE,
output wire i2c1_sda_OUT,
2024-09-04 14:42:45 +02:00
enjoy-digital
eda553aeaa
Merge pull request #2056 from trabucayre/altera_agilex5_asyncresetsynchronizer
...
build/altera/common: added special AsyncResetSynchronizer based on altera_std_synchronizer_nocut
2024-09-03 17:54:27 +02:00
Gwenhael Goavec-Merou
d0215001f4
build/altera/common: added special AsyncResetSynchronizer based on altera_std_synchronizer_nocut
2024-09-03 17:47:40 +02:00
Dolu1990
a90ab9dcca
efinix: Merge pt.sdc to the litex sdc to get constraints right
2024-09-03 12:05:26 +02:00
Florent Kermarrec
dc29b6f4e5
CHANGES.md: Update.
2024-09-03 09:44:28 +02:00
Gwenhael Goavec-Merou
4152d22065
Revert "build/efinix/platform: fix get_pin_name()"
...
This reverts commit 0cb101da25
2024-09-03 10:24:38 +02:00
Dolu1990
3de5832b9c
vexiiriscv: Now use pll.locked for debug reset
2024-09-03 07:58:24 +02:00
Dolu1990
19b3f24d9f
efinix: ifacewriter support drive strength and slew
2024-09-03 07:57:30 +02:00
Dolu1990
e01ce6f948
efinix: ifacewriter support drive strength and slew
2024-09-03 07:55:25 +02:00
Florent Kermarrec
3bdbe1ebcf
CHANGES.md: Update.
2024-09-02 14:20:09 +02:00
enjoy-digital
af0dc7f98b
Merge pull request #2055 from trabucayre/gowin_apicula_fix
...
Gowin apicula fix
2024-09-02 14:08:07 +02:00
Gwenhael Goavec-Merou
babe233407
build/gowin/apicula: only append _packer_opts with known use_xxx (drop options only required by Gowin's software)
2024-09-01 09:55:01 +02:00
Gwenhael Goavec-Merou
3da470048a
build/gowin/apicula: append _synth_opts with specific requirements according to FPGA model
2024-09-01 09:53:24 +02:00
Dolu1990
2f2b292e06
vexii add with-cpu-clk
2024-08-30 18:16:56 +02:00
enjoy-digital
15cd556750
Merge pull request #2053 from enjoy-digital/hyperram_new
...
soc/cores/hyperbus: Full rewrite of HyperRAM core.
2024-08-30 15:38:59 +02:00
Florent Kermarrec
61b54aa491
soc/integration/soc: Fix add_peripheral.
2024-08-30 12:08:00 +02:00
Florent Kermarrec
c554752e8a
soc/cores/hyperbus: Add automatic read burst detection.
2024-08-30 11:53:14 +02:00
Dolu1990
c14f1d0816
vexiiriscv add video support
2024-08-30 10:44:36 +02:00
Dolu1990
5fb873d209
efinix: Add support for more IO
2024-08-30 10:44:10 +02:00
Florent Kermarrec
3bde3e9848
soc/cores/hyperbus: Add automatic write burst detection.
2024-08-29 19:20:23 +02:00
Florent Kermarrec
fac80c3a51
soc/cores/hyperbus: Full rewrite of HyperRAM core.
...
Rewriting the HyperRAM core to improve its design and functionality. The
old core grew complex over time without a clear structure. This new version
offers:
- IO registers on all signals for better performance.
- Flexible clocking options.
- Simplified architecture.
- Easier to extend with new features.
This rewrite provides a base for future development.
2024-08-29 12:54:09 +02:00
Dolu1990
cc3f13670a
Merge pull request #2050 from Dolu1990/efinix_pll_ext_fix
...
efinix: Fix PLL with external clock input ifacewriter
2024-08-28 20:13:03 +02:00
Dolu1990
d4003b8cfa
efinix add SCHMITT_TRIGGER support
2024-08-28 19:59:30 +02:00
Gwenhael Goavec-Merou
4ded509444
Merge pull request #2050 from Dolu1990/efinix_pll_ext_fix
...
efinix: Fix PLL with external clock input ifacewriter
2024-08-27 09:50:04 +02:00
Gwenhael Goavec-Merou
f8feb8a192
Merge pull request #2048 from trabucayre/colognechip_improve
...
Colognechip improve
2024-08-27 09:49:15 +02:00
Dolu1990
6d46a5ba05
efinix: Fix PLL with external clock input ifacewriter
2024-08-27 09:02:58 +02:00
Gwenhael Goavec-Merou
0fcc27f58f
build/colognechip/colognechip.py: simplify constrains file with the new toolchain
2024-08-24 12:20:58 +02:00
Gwenhael Goavec-Merou
07e11858c6
soc/cores/clock/colognechip.py: rework/fix locked signal
2024-08-24 12:19:34 +02:00
Gwenhael Goavec-Merou
ef775e0b8e
Merge pull request #2043 from pepijndevos/moreapicula
...
fixes for apicula support
2024-08-24 10:37:17 +02:00
Pepijn de Vos
4400fbb966
Apicula: add GWINR-18 aliases
2024-08-22 16:02:41 +02:00
enjoy-digital
6d0ae25d65
Merge pull request #2046 from enjoy-digital/hyperbus_2x
...
HyperRAM: Add 2:1 ratio support in addition of 4:1 ratio.
2024-08-21 19:25:41 +02:00
Florent Kermarrec
a88cee70c8
test/test_hyperbus: Update.
2024-08-21 19:22:56 +02:00
Florent Kermarrec
37823e34b6
soc/cores/hyperbus: Simplify Clk Generation.
2024-08-21 17:10:36 +02:00
Florent Kermarrec
ecd9eee5a4
soc/core/hyperbus: Report Clk Ratio on Status register and use it in software to configure latency.
2024-08-21 15:35:21 +02:00
Florent Kermarrec
5587f5954d
test/test_hyperbus: Add 2:1 test.
2024-08-21 15:00:11 +02:00
Florent Kermarrec
d22669cf05
soc/cores/hyperbus: Handle 4:1/2:1 specific cases separately, default to 4:1 mode (as before).
2024-08-21 12:07:55 +02:00
Florent Kermarrec
f6de6e755e
soc/cores/hyperbus: Add cd_io/sync_io.
2024-08-21 11:50:46 +02:00
Florent Kermarrec
43879b0f73
soc/cores/hyperbus: Add clk_ratio support to support x1/x2.
2024-08-21 11:41:13 +02:00
Florent Kermarrec
22afa34a64
soc/cores/hyperbus: WiP to make increase similarities between x1/x2 versions.
2024-08-21 11:17:55 +02:00
Florent Kermarrec
50f0a1057c
soc/cores/hyperbus: Do some tests with sys_2x, seems working.
2024-08-21 10:57:36 +02:00
Florent Kermarrec
0b028d3956
soc/cores/hyperbus: Add comment to allow switching to SDRTristate.
2024-08-20 22:05:38 +02:00
Florent Kermarrec
60f83b71fa
soc/cores/hyperbus: Avoid dq_oe condition to generate dq_o (was only useful for sim but now avoided).
2024-08-20 21:54:15 +02:00
enjoy-digital
298a004f08
Merge pull request #2045 from enjoy-digital/hyperbus_io_regs
...
Improve HyperRAM core to allow IO Reg inference.
2024-08-20 19:47:01 +02:00
Florent Kermarrec
3a37d3ba98
software/libbase/hyperram: Add missing #ifdef.
2024-08-20 17:11:02 +02:00
Florent Kermarrec
eb29b40e07
soc/cores/hyperbus: Simplify CS and make it synchronous to allow IO Reg.
2024-08-20 16:19:15 +02:00
Florent Kermarrec
1998c74549
soc/cores/hyperbus: Make DQ/RWDS input sync explicit to allow IO Reg.
2024-08-20 15:44:53 +02:00
Florent Kermarrec
8b86b16077
soc/cores/hyperbus: Make Rst synchronous to allow IO Reg (even if low speed).
2024-08-20 15:26:26 +02:00
