26963d62fa
libnet/microudp: (WIP) fix endianness issues
2018-09-06 18:43:55 +02:00
d9d0320d7c
Merge pull request #98 from jfng/fix_typo
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fix typo and unused include
2018-09-06 18:23:29 +02:00
22c0131324
fix typo and unused include
2018-09-06 17:07:14 +02:00
fb24ac0ecc
cpu/minerva: add workaround on import until code is released
2018-09-06 16:40:30 +02:00
9cfae4dfde
setup.py: create litex_sim exec to ease simulation
2018-09-06 08:48:14 +02:00
8f377307d8
add Minerva support
2018-09-05 22:33:04 +02:00
1944289e64
litex_server: update pcie and remove bar_size parameter
2018-09-05 13:01:51 +02:00
c5a2d6f3ec
Merge pull request #96 from cr1901/tinyfpga_bx
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build/platforms: Add TinyFPGA BX board and programmer.
2018-09-03 20:49:33 -07:00
2949262449
build/platforms: Add TinyFPGA BX board and programmer.
2018-09-03 23:39:40 -04:00
3cb754da74
Merge pull request #95 from cr1901/lm32-lite
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Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly.
2018-09-03 20:13:45 -07:00
ed507d618d
Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly.
2018-09-03 19:48:19 -04:00
28cd2da24e
README: update
2018-08-31 08:44:22 +02:00
05c7b9daf4
Merge pull request #94 from cr1901/nextpnr
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lattice/icestorm: Add nextpnr pnr as alternate pnr tool.
2018-08-28 11:46:35 +02:00
7af89efc70
lattice/icestorm: Add nextpnr pnr as alternate pnr tool.
2018-08-28 05:17:32 -04:00
7a14b75cd6
Merge pull request #93 from phlipped/master
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Fix URL for liteUSB
2018-08-24 14:08:28 +10:00
8b51c44506
Fix URL for liteUSB
2018-08-24 14:03:16 +10:00
0074bb888c
Merge pull request #91 from cr1901/ignore-fix
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.gitignore: litex/build contains valid source, so exclude from .gitig…
2018-08-23 13:17:40 +10:00
ff908e404f
Merge pull request #92 from cr1901/l2-gate
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software/bios: Gate flush_l2_cache() if L2 Cache isn't present.
2018-08-23 13:15:49 +10:00
dd480eb72c
.gitignore: litex/build contains valid source, so exclude from .gitignore.
2018-08-22 23:04:20 -04:00
3146109af3
software/bios: Gate flush_l2_cache() if L2 Cache isn't present.
2018-08-22 23:03:08 -04:00
759e7d4dc3
bios/sdram: improve/simplify read window selection
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Compute a score for each window and select the best
2018-08-22 23:15:32 +02:00
09776b77e6
sim: run as root only when needed (ethernet module present)
2018-08-22 15:20:28 +02:00
06e835a3f8
builder: change call to get_sdram_phy_c_header and also pass timing_settings
2018-08-22 14:28:37 +02:00
ee26f8c5ae
soc_sdram: cosmetic
2018-08-22 13:40:22 +02:00
2db5424ae6
soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >)
2018-08-22 13:28:23 +02:00
45e9a42c7e
soc_core: add cpu_endianness
2018-08-21 19:10:22 +02:00
3877d0f111
builder: get_sdram_phy_header renamed to get_sdram_phy_c_header
2018-08-21 18:15:57 +02:00
c64e44ef3f
soc_sdram: use new LiteDRAMWishbone2Native and port.data_width
2018-08-21 14:52:28 +02:00
2eeccc5054
vexriscv: update
2018-08-21 11:04:15 +02:00
eecc6f68ed
soc/integration: move sdram_init to litedram
2018-08-20 15:36:51 +02:00
077f939169
Vexriscv: update csr-defs.h
2018-08-18 14:15:43 +02:00
4225c3b87c
update Vexriscv
2018-08-18 14:14:00 +02:00
9547938527
bios/sdram: changes to ease manual read window selection
2018-08-18 13:45:22 +02:00
a760322fbd
litex_server: allow multiple clients to connect to the same server
2018-08-17 16:09:08 +02:00
8a69a47e7b
cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40)
2018-08-17 08:32:32 +02:00
cb5b4ac468
bios/boot: flush all caches before running from ram
2018-08-16 19:47:43 +02:00
650ac18685
sim/verilator: catch ctrl-c on exit and revert default termios settings
2018-08-16 15:13:27 +02:00
0831ad5492
cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf
2018-08-16 10:04:09 +02:00
1610a7f3fb
bios/sdram: fix read_level_scan result
2018-08-14 18:33:36 +02:00
e07ca05749
Merge pull request #86 from pgielda/patch-1
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Fix generating csr.csv file
2018-08-12 19:34:52 +02:00
3c7890cdd4
Fix generating csr.csv file
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Fix generating csr.csv file when no absolute path is given.
2018-08-12 13:37:39 +02:00
9fa234da50
soc/intergration/cpu_interface: typo
2018-08-08 08:53:54 +02:00
22f645adc1
bios/main: use edata instead of erodata
2018-08-07 09:02:09 +02:00
580efecc8c
picorv32: add reset signal
2018-08-07 08:59:34 +02:00
0429ee9f8f
soc/software/bios: add reboot command
2018-08-06 12:23:50 +02:00
da75159814
soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers
2018-08-06 12:23:16 +02:00
8ba5625227
soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error.
2018-08-06 12:21:18 +02:00
c0989f65dd
soc/cores/cpu: add reset signal
2018-08-06 12:19:23 +02:00
380f8b96dd
Merge pull request #81 from xobs/vexriscv-to-wishbone
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Push Vexriscv debug directly on the Wishbone bus
2018-07-27 11:59:28 +02:00
fb145daced
tools: remove vexriscv_debug
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This program is no longer needed.
The `openocd_vexriscv` package natively supports `etherbone`, and now
that the vexriscv debug module is available on Wishbone instead of as a
CSR, this module no longer works.
This change simplifies both tooling (because there is one fewer program
to run) and integration (because you don't need to modify your CSRs
anymore, just `register_mem()`.)
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-27 15:25:33 +08:00
Jean-François Nguyen
enjoy-digital
Jean-François Nguyen
Jean-François Nguyen
Tim Ansell
William D. Jones
phlipped
Peter Gielda
Sean Cross