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2 commits

Author SHA1 Message Date
Sebastien Bourdeauducq
7b8e8a19f3 Support adding Verilog/VHDL files 2013-02-08 20:25:20 +01:00
Sebastien Bourdeauducq
fb5130fc1f Initial version 2013-02-07 22:07:30 +01:00