Sebastien Bourdeauducq
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2bbcc218f3
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sim: fix case break
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2015-10-20 17:18:33 +08:00 |
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Sebastien Bourdeauducq
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60ae9dce0d
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sim: do not use py35 collections.Generator
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2015-10-20 16:37:54 +08:00 |
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Sebastien Bourdeauducq
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ac5271e80e
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sim: truncate case test value
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2015-10-19 20:08:46 +08:00 |
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Sebastien Bourdeauducq
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1f89900b16
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sim: generators are also iterables...
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2015-10-19 19:21:20 +08:00 |
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Sebastien Bourdeauducq
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02d804feab
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sim: accept iterables as generator list
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2015-10-19 19:18:17 +08:00 |
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Sebastien Bourdeauducq
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0999a17319
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verilog, sim: accept iterables in FHDL statements
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2015-10-19 19:17:26 +08:00 |
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Sebastien Bourdeauducq
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a824046bbc
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Revert "sim/core: fix Cat bitshift"
This reverts commit 6d6f91a02b.
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2015-10-19 16:08:42 +08:00 |
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Sebastien Bourdeauducq
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6d6f91a02b
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sim/core: fix Cat bitshift
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2015-10-19 16:07:45 +08:00 |
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Sebastien Bourdeauducq
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28962ff438
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sim/core: truncate evaluated values before test in If
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2015-10-19 15:58:21 +08:00 |
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Sebastien Bourdeauducq
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4acb7bc662
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sim: support execution of nested statement lists (typo)
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2015-10-15 13:53:04 +08:00 |
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Sebastien Bourdeauducq
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3b7f1264f1
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sim: support execution of nested statement lists
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2015-10-15 13:52:24 +08:00 |
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Sebastien Bourdeauducq
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e0899c1424
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sim: make sure replaced memory signals are always in VCD signal set
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2015-10-05 12:24:32 +08:00 |
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Sebastien Bourdeauducq
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808cf06add
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fhdl: replace flen with len
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2015-09-26 18:45:10 +08:00 |
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Sebastien Bourdeauducq
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8534562185
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sim: fix slice assign
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2015-09-22 20:33:44 +08:00 |
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Sebastien Bourdeauducq
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2c1553fea2
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sim: insert resets, support ClockSignal and ResetSignal
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2015-09-21 22:13:36 +08:00 |
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Sebastien Bourdeauducq
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99af825a5a
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sim: drive clock signals
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2015-09-21 21:53:41 +08:00 |
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Sebastien Bourdeauducq
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a67b4baa0c
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sim: VCD output support
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2015-09-21 21:20:31 +08:00 |