2f769e4e4e
gtx: add resynchronization on control signals
2014-09-27 17:26:05 +02:00
f23c5aa724
mmcm: configure default divider with default_speed
2014-09-27 16:22:40 +02:00
45f7f8aff5
add tx_reset_fsm and rx_reset_fsm
2014-09-27 16:10:39 +02:00
c27f24c4c0
reorganize code
...
- use sys_clk of 166.66MHz and using it instead of sata clk.
- rename clocking to CRG since it also handles resets.
- create datapath and move code from gtx.
2014-09-27 15:34:28 +02:00
879478a6e4
clocking: clean up and add comments
2014-09-27 13:33:43 +02:00
387cf90cf8
host and device communicate with OOB, now need to fix ctrl
2014-09-26 23:30:30 +02:00
01da43ecb2
reset and lock of PLL OK. We see OOB signals on the link but they are not decoded by the device.
2014-09-26 22:31:32 +02:00
dfbec91a62
add modelsim simulation and start fixing init
2014-09-26 17:05:05 +02:00
7e14c4fc51
move some logic outside of GTX
2014-09-25 15:23:56 +02:00
c008dfdd98
clean up (thanks to Sebastien)
2014-09-25 14:17:25 +02:00
435bc22fa0
integrate phy in test design and start fix syntax errors
2014-09-24 16:07:34 +02:00
18009303ae
instanciate device or host controller
2014-09-24 14:00:00 +02:00
60324295fa
manage clock domain crossing and data width conversion in gtx
2014-09-24 13:56:12 +02:00
f436069a04
create sata clock (sata_tx/2 for a 32 bits data path)
2014-09-24 13:55:06 +02:00
7790105913
realign rxdata / rxcharisk directly in gtx
2014-09-24 12:13:43 +02:00
f74471d027
add device ctrl skeleton (we will use it for simulation with the host)
2014-09-24 11:37:28 +02:00
d78cae1b57
more ctrl skeleton
2014-09-24 11:07:36 +02:00
71bfd036d0
add ctrl skeleton
2014-09-24 00:01:01 +02:00
fa509b3365
rearrange code and remove datapath for now
2014-09-23 23:03:32 +02:00
Florent Kermarrec