c27f24c4c0
reorganize code
...
- use sys_clk of 166.66MHz and using it instead of sata clk.
- rename clocking to CRG since it also handles resets.
- create datapath and move code from gtx.
2014-09-27 15:34:28 +02:00
879478a6e4
clocking: clean up and add comments
2014-09-27 13:33:43 +02:00
1d053bd7ee
modify TestDesign to be able to simulate phy with host <--> device loopback
2014-09-25 15:37:49 +02:00
435bc22fa0
integrate phy in test design and start fix syntax errors
2014-09-24 16:07:34 +02:00
7e31ef2152
init with repo with simple TestDesign
2014-09-22 13:36:43 +02:00
Florent Kermarrec