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1,500 Commits 40 Branches 14 Tags 51 MiB
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1500 Commits

Author SHA1 Message Date
Florent Kermarrec 1d053bd7ee modify TestDesign to be able to simulate phy with host <--> device loopback 2014-09-25 15:37:49 +02:00
Florent Kermarrec 7e14c4fc51 move some logic outside of GTX 2014-09-25 15:23:56 +02:00
Florent Kermarrec c008dfdd98 clean up (thanks to Sebastien) 2014-09-25 14:17:25 +02:00
Florent Kermarrec 111f527647 do some clean up 2014-09-24 22:26:33 +02:00
Florent Kermarrec 2fb418a373 use new MiSoC UART with phase accumulators 
this will allow to speed up MiLa reads
 2014-09-24 21:56:15 +02:00
Florent Kermarrec 435bc22fa0 integrate phy in test design and start fix syntax errors 2014-09-24 16:07:34 +02:00
Florent Kermarrec 18009303ae instanciate device or host controller 2014-09-24 14:00:00 +02:00
Florent Kermarrec 60324295fa manage clock domain crossing and data width conversion in gtx 2014-09-24 13:56:12 +02:00
Florent Kermarrec f436069a04 create sata clock (sata_tx/2 for a 32 bits data path) 2014-09-24 13:55:06 +02:00
Florent Kermarrec 7790105913 realign rxdata / rxcharisk directly in gtx 2014-09-24 12:13:43 +02:00
Florent Kermarrec f74471d027 add device ctrl skeleton (we will use it for simulation with the host) 2014-09-24 11:37:28 +02:00
Florent Kermarrec d78cae1b57 more ctrl skeleton 2014-09-24 11:07:36 +02:00
Florent Kermarrec 71bfd036d0 add ctrl skeleton 2014-09-24 00:01:01 +02:00
Florent Kermarrec fa509b3365 rearrange code and remove datapath for now 2014-09-23 23:03:32 +02:00
Florent Kermarrec 22ea5b08b0 clean up and add K7SATAGTXReconfig skeleton (empty but we don't need it for now) 2014-09-23 22:40:01 +02:00
Florent Kermarrec 674e0b3581 remove GTXE2_COMMON (we use in fact CPLL and not QPLL, GTXE2_COMMON was here in design just because of an old ISE bug) 
(see http://www.xilinx.com/support/answers/45410.html for more information)
 2014-09-23 22:17:08 +02:00
Florent Kermarrec e0fd313ce0 add data path from another design (need to be adapted to SATA specification) 2014-09-23 17:36:11 +02:00
Florent Kermarrec d55db1688b add SATAGTX with RX/TX clocking and reset (no DRP for now) 2014-09-23 17:18:03 +02:00
Sebastien Bourdeauducq 410f250d2a software: remove setjmp 2014-09-23 21:57:05 +08:00
Florent Kermarrec cbbbf8de8b add dict for fbdiv computation on GTXE2_COMMON 2014-09-23 14:11:14 +02:00
Florent Kermarrec 4aff15bb74 create k7satagtx.py and move GTXE2 primitive inside 2014-09-23 14:03:51 +02:00
Florent Kermarrec 7422b94f90 create GTXE2_CHANNEL & GTXE2_COMMON class / add IO signals and parameters 2014-09-23 13:57:02 +02:00
Florent Kermarrec 1a5a2d10e3 fill GTXE2_COMMON constants parameters and signals for SATA / disconnect unused output ports 2014-09-23 12:01:57 +02:00
Florent Kermarrec fc64b44391 fill GTXE2_CHANNEL constants parameters and signals for SATA / disconnect unused output ports 2014-09-23 11:54:36 +02:00
Florent Kermarrec ac8d8783cf k7sataphy: add GTXE2_COMMON instance skeleton 2014-09-23 10:23:54 +02:00
Florent Kermarrec bdf038f241 k7sataphy: add GTXE2_CHANNEL instance skeleton 2014-09-23 10:08:17 +02:00
Florent Kermarrec 7e31ef2152 init with repo with simple TestDesign 2014-09-22 13:36:43 +02:00
Sebastien Bourdeauducq 14d53526be libbase: use __builtin_setjmp and __builtin_longjmp 2014-09-21 17:43:17 +08:00
Sebastien Bourdeauducq 503a2f00b5 mor1kx: sync 2014-09-12 16:00:32 +08:00
Florent Kermarrec c0c17030fd spi_flash: simplify usage by removing cmd, cmd_width, addr_width parameters 2014-09-04 15:23:39 +08:00
Sebastien Bourdeauducq 36434b62f0 sdram: merge DFII_PIX_RDDATA_SIZE and DFII_PIX_WRDATA_SIZE 2014-09-03 15:02:38 +08:00
Sebastien Bourdeauducq 2388bfabc3 bios: support DDR3 write leveling and read calibration. This makes the full DDR3 SODIMM work on the KC705. 2014-09-03 14:25:26 +08:00
Sebastien Bourdeauducq a7b4550e59 sdramphy/initsequence: cleanup and expose DDR3 MR1 value 2014-09-03 14:21:30 +08:00
Florent Kermarrec 114890ee80 sdramphy/initsequence: clean up mr1/mr2 computation on DDR3 and enable Dynamic ODT 2014-09-02 10:54:29 +08:00
Sebastien Bourdeauducq 2234f50223 k7ddrphy: add bitslip control for incoming DQ 2014-09-01 19:54:39 +08:00
Sebastien Bourdeauducq 0eeb0ad9eb targets/kc705: add ddrphy to CSR map 2014-09-01 16:40:10 +08:00
Sebastien Bourdeauducq 6decb357f1 bios: add sdrrderr 2014-09-01 15:23:37 +08:00
Sebastien Bourdeauducq 57335bdf3f bios: add DQ filtering to sdrrd, add sdrrdbuf command 2014-09-01 14:58:58 +08:00
Sebastien Bourdeauducq 5483b37c8f k7ddrphy: write leveling and read calibration support 2014-08-31 21:54:28 +08:00
Sebastien Bourdeauducq 19abe2b888 k7ddrphy: do not register T at SERDES (fixes timing problem) 2014-08-31 21:53:35 +08:00
Sebastien Bourdeauducq a2096ff083 libcompiler-rt: add moddi3 2014-08-28 16:54:12 +08:00
Sebastien Bourdeauducq 541e5abbc7 k7ddrphy: update comment 2014-08-22 19:02:57 +08:00
Sebastien Bourdeauducq 66fe45ba96 k7ddrphy: decrease CAS latency to account for cmd/data flight time 2014-08-22 18:46:01 +08:00
Sebastien Bourdeauducq b94647ab16 k7ddrphy: suppress idiotic bitgen warning about ISERDES IOBDELAY parameter 2014-08-22 18:45:25 +08:00
Sebastien Bourdeauducq 35327a427f targets/kc705: BIOS XIP 2014-08-22 17:13:10 +08:00
Sebastien Bourdeauducq 6b35c7b8ea targets/ppro: reduce SPI flash clock frequency 2014-08-22 15:24:14 +08:00
Sebastien Bourdeauducq 7b10f1821f targets/ppro: fix BIOS address 2014-08-22 15:24:00 +08:00
Florent Kermarrec 3eabec28cd make.py: add set_flash_proxy_dir to flash-bios 2014-08-22 15:04:50 +08:00
Sebastien Bourdeauducq 2f2a57dd34 targets/ppro: clean up indentation 2014-08-22 14:41:28 +08:00
Florent Kermarrec 1c381acc6f k7ddrphy: fix read_latency (CL is 2 sys_clk since we use quarter rate) 2014-08-14 22:46:06 +08:00