Commit Graph

6257 Commits

Author SHA1 Message Date
Piense e441bd60fa build/lattice: add initial Radiant support for NX FPGA family (Crosslink-NX/Certus-NX). 2020-08-24 16:23:22 +02:00
enjoy-digital 8a44464a45
Merge pull request #640 from antmicro/mor1kx_dt
litex_json2dts: Add support for mor1kx
2020-08-24 14:26:11 +02:00
Florent Kermarrec 4f1c32abdc targets/de0nano: set sys2x_ps to 180° for sdram_rate=1:2. 2020-08-24 09:30:38 +02:00
Florent Kermarrec d16051ff90 boards/ulx3s: keep up to date with litex-boards. 2020-08-24 09:08:30 +02:00
Florent Kermarrec d826c60658 soc/cores/clock/ECP5PLL: specificy CLKOS3_F/CPHASE and -1 on cphase to match Clarity Designer values. 2020-08-24 09:04:33 +02:00
Florent Kermarrec 9e37b16ec0 soc/interconnect/axi/AXILite2CSR: add register parameter for genericity.
Not yet used, but simplify SoC integration.
2020-08-24 09:03:04 +02:00
Mateusz Holenko 4dab1eb0c8 litex_json2dts: Add support for mor1kx 2020-08-24 08:02:16 +02:00
Florent Kermarrec 42d8fc226a Merge branch 'master' of https://github.com/enjoy-digital/litex 2020-08-23 15:42:39 +02:00
Florent Kermarrec 77ae243310 test: add SPDX License identifier to header and specify file is part of LiteX. 2020-08-23 15:40:21 +02:00
Florent Kermarrec b8371ef480 tools: add SPDX License identifier to header and specify file is part of LiteX. 2020-08-23 15:37:16 +02:00
Florent Kermarrec 93d906f9d1 soc: add SPDX License identifier and specify file is part of LiteX. 2020-08-23 15:33:01 +02:00
Florent Kermarrec e52ffd2da0 gen: add specify SPDX License identifier and specify file is part of Migen and has been modified/adapted for LiteX. 2020-08-23 15:19:46 +02:00
Florent Kermarrec 70610b2332 build: add SPDX License identifier and specify file is part of LiteX. 2020-08-23 15:14:45 +02:00
Florent Kermarrec 6ee882d1ec platforms/targets: add SPDX License identifier to header and specify file is part of LiteX. 2020-08-23 15:08:15 +02:00
enjoy-digital ee0e240242
Merge pull request #631 from gsomlo/gls-abc9-fixup
build/lattice/trellis: make "-abc9" an optional argument
2020-08-22 20:06:57 +02:00
Florent Kermarrec 9950e75654 build/io: fix InferedSDRIO (thanks @mtdudek). 2020-08-22 19:49:34 +02:00
enjoy-digital bae871a884
Merge pull request #632 from gsomlo/gls-sdcard-refactor
refactor sdcard (bios) software
2020-08-22 19:44:59 +02:00
enjoy-digital 3206dba911
Merge pull request #636 from Xiretza/minerva-cli-filetype
Fix call to generation of minerva output file
2020-08-22 19:41:07 +02:00
enjoy-digital 8bc5dd7c8c
Merge pull request #635 from Xiretza/collections-abc-deprecation
Fix DeprecationWarning for collections.abc
2020-08-22 19:40:44 +02:00
enjoy-digital 7984436248
Merge pull request #634 from betrusted-io/spi_opi_timing_only
add a pipe register to relax an async_default timing path
2020-08-22 19:39:51 +02:00
Xiretza e3bb3a9488
Fix call to generation of minerva output file
With nmigen/nmigen#a7b8ced, cli.py no longer defaults to generating
verilog code, so -t/--type has to be specified explicitly.

$ pytest test/test_targets.py -k test_variants_minerva
[...]
cli.py: error: specify file type explicitly with -t
2020-08-22 14:54:40 +02:00
Xiretza fcc7058bfc
Fix DeprecationWarning for collections.abc
DeprecationWarning: Using or importing the ABCs from 'collections' instead of from 'collections.abc' is deprecated since Python 3.3, and in 3.9 it will stop working
2020-08-22 13:39:30 +02:00
bunnie d783e86ff6 add a pipe register to relax an async_default timing path
there is an async reset signal going to a FIFO
that can't be false_path'd because its timing is important
to making sure that the burst FIFO is reset to zero when
a miss happens in the burst cache. Unfortunately as designs
get full, the routability of this signal becomes difficult
and drives up the compile time and reduces quality of results.

There is enough time in the design to insert a single pipe stage
to alleviate the timing somewhat. This commit adds that register.
2020-08-20 04:14:10 +08:00
Gabriel Somlo e0b2b8153f liblitesdcard/sdcard: read sdcard response only when needed
Instead of reading the 128 byte sdcard response after each operation,
read it only during debugging and/or when it's necessary (to retrieve
the relative card address, rca).

We no longer need a global sdcard_response array, and refactor the
various retrieval and reporting functions to contain a local buffer
for that purpose, only if/when necessary.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-08-17 18:45:24 -04:00
Gabriel Somlo a47b2de5fe sdcard: refactor command functions
Factor out common portion of command functions. Also use appropriate
unsigned int width (e.g., uint16_t) for arguments.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-08-17 18:45:24 -04:00
Gabriel Somlo bfd6b3c3f4 liblitesdcard/sdcard: cosmetic fixes (indentation, #ifdef, etc.) 2020-08-17 18:45:24 -04:00
Gabriel Somlo 37ebcd3be7 factor out busy_wait_us() 2020-08-17 18:45:24 -04:00
Gabriel Somlo c4710b371a build/lattice/trellis: make "-abc9" an optional argument
Fix up earlier commit (#6c298cb7) and make the '-abc9' optional
argument to yosys' synth_ecp5 actually optional (and off by default)
in LiteX's trellis build infrastructure.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-08-15 16:49:08 -04:00
Florent Kermarrec 35929c0f8a soc/integration/csr_bridge: use registered version only when SDRAM is present.
Seems to be a good compromise for now.
2020-08-14 15:29:49 +02:00
Florent Kermarrec e4f5dd987e interconnect/wishbone/Wishbone2CSR: add registered version and use it as default. 2020-08-14 00:47:05 +02:00
Florent Kermarrec b344196aba build/lattice/diamond: use diamondc instead of pnmainc (avoid having to set environment variables).
http://www.latticesemi.com/en/Support/AnswerDatabase/5/5/2/5522
2020-08-14 00:10:56 +02:00
Dolu1990 f730f1d7ba
cores/cpu/vexriscv_smp fix argument parsing 2020-08-13 12:52:05 +02:00
Florent Kermarrec 0e480dd662 bios/main/sdram: fix speed reporting (Mbps/pin not MHz). 2020-08-11 22:13:14 +02:00
enjoy-digital bb7f33434e
Merge pull request #627 from gsomlo/gls-dma-addr-64
RFC: cores/dma, liblitesdcard/sdcard: use 64 bits for dma base address
2020-08-10 21:44:02 +02:00
Gabriel Somlo ba34c85284 cores/dma, liblitesdcard/sdcard: use 64 bits for dma base address
Make the DMA base address register 64-bit wide, to cover situations
in which the physical memory being accessed is above the 4GB limit
(e.g., on 64-bit systems with more than 4GB of provisioned physical
memory).

Also update DMA reader/writer setup call sites in the bios (currently
only used by litesdcard).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-08-10 14:09:25 -04:00
Florent Kermarrec 4cf28a0107 software/bios: display SDRAM databits and freq. 2020-08-07 19:49:02 +02:00
Florent Kermarrec 6f69679d21 cpu/vexriscv_smp: more coherent_dma to __init__ instead of add_memory_buses.
LiteX is creating the SoC.dma_bus just after the CPU is declared, so declaring it in add_memory_buses was preventing it.
It's also more coherent to move it to __init__ since not related to the memory_buses.
2020-08-07 14:47:21 +02:00
Florent Kermarrec b3531cd2a8 cores/cpu: add external cpu_type.
Allows fully pluggable CPUs where cpu_type is set to "external" and cpu_cls provided externally.
2020-08-07 11:16:00 +02:00
Florent Kermarrec b9d3aab59d targets: use platform.request_all on LedChaser. 2020-08-06 20:02:17 +02:00
Florent Kermarrec 14c9166429 build/generic_platform: add request_all method. 2020-08-06 20:00:07 +02:00
Florent Kermarrec 57335b9971 cores/cpu/zynq7000: simplify using new loose parameter of Platform.request.
And avoid the try/except that can mask others errors.
2020-08-06 19:44:46 +02:00
enjoy-digital 4867f2b324
Merge pull request #624 from trabucayre/emio_zynq
soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode
2020-08-06 19:34:03 +02:00
Florent Kermarrec 48d63f2362 build/generic_plaform: add loose parameter to return None when not available/existing.
Similar to loose parameter already present on Platform.lookup_request.
2020-08-06 19:33:04 +02:00
enjoy-digital 81df7b7036
Merge pull request #625 from scanakci/blackparrot_litex
Blackparrot human name change (IMA), minor transducer fix
2020-08-06 18:50:39 +02:00
Florent Kermarrec 188e6f573a integration/soc/add_etherbone: pass phy to ethcore not self.ethphy.
Similar in most of the cases but added restrictions.
2020-08-06 18:23:04 +02:00
sadullah 2457859b2d update BlackParrot transducer 2020-08-06 12:21:38 -04:00
sadullah d2dabcef9a Blackparrot human name update 2020-08-06 12:21:38 -04:00
Gwenhael Goavec-Merou 87c26a30fd soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode 2020-08-06 16:45:39 +02:00
enjoy-digital d5062d1f4f
Merge pull request #623 from Dolu1990/vexriscv_smp
cpu/vexriscv_smp Add --with-coherent-dma  --without-coherent-dma
2020-08-06 14:31:20 +02:00
Dolu1990 07a8e696ce cpu/vexriscv_smp Add --with-coherent-dma 2020-08-06 13:33:11 +02:00