Robert Jordens
94a2499ce5
AutoCSR: refactor common gatherer code
2015-09-06 20:00:14 -07:00
Sebastien Bourdeauducq
f1dc008d32
Simulator will be rewritten
2015-09-05 15:07:00 -06:00
Sebastien Bourdeauducq
dec2e23fc7
Remove code that will be into MiSoC or other packages.
2015-09-05 15:06:04 -06:00
Florent Kermarrec
7363f00867
mibuild/altera/common: use Altera instead of Quartus (coherency with xilinx/common)
2015-09-05 15:47:56 +02:00
Florent Kermarrec
bedf3ed9a6
misoclib/soc: fix add_constant when used for strings
2015-09-01 16:57:50 +02:00
Florent Kermarrec
a4808ace6f
litecores: remove unneeded AutoCSR inheritance in example designs (thanks William D. Jones)
2015-08-26 22:36:48 +02:00
Florent Kermarrec
e91ce85cfd
litescope/core/port: fix missing self.comb...
2015-08-24 20:12:39 +02:00
Florent Kermarrec
27b1dd7d9e
litescope/core/port: fix EdgeDetector CSRs names
2015-08-24 19:40:53 +02:00
Florent Kermarrec
fd31e6ae61
litescope/core/port: fix LiteScopeEdgeDetector (refactoring issues)
2015-08-24 18:23:38 +02:00
Florent Kermarrec
f3d68a54d5
liteth/phy: simplify clk_freq in LiteEthPHY autodetect function (thanks Sebastien)
2015-08-22 16:30:42 +02:00
Florent Kermarrec
a1e4183b3f
sdram/phy/s6ddrphy: fix comment on S6QuarterRateDDRPHY
2015-08-22 12:50:41 +02:00
Florent Kermarrec
de87d65f68
sdram/module: add P3R1GE4JGF DDR2 (Atlys) and MT41J128M16 DDR3 (Opsis, Novena) modules.
2015-08-22 12:42:44 +02:00
Florent Kermarrec
50e857e99c
sdram/phy/s6ddrphy: add S6QuarterRateDDRPHY to run DDR3 at higher frequencies.
...
Built on top of S6HalfRateDDRPHY, exposes a 4 phases DFI interface to the controller with a 2x slower clock.
Validated on the Numato Lab opsis board (50MHz sys_clk/ DDR400), should also work on the Novena laptop (same DDR3 module).
2015-08-22 12:17:48 +02:00
Florent Kermarrec
8bb30a8620
liteeth/phy: fix autodetect (clk_freq not necessary passed in kwargs)
2015-08-22 12:08:49 +02:00
Florent Kermarrec
158fbe49ac
sdram/phy/s6ddrphy: rename S6DDRPHY to S6HalfRateDDRPHY and use ORed wrdata_en/rddata_en (the controller already manages that)
2015-08-22 11:47:26 +02:00
Florent Kermarrec
b8f3fd53f1
README: small update
2015-08-22 11:39:54 +02:00
Florent Kermarrec
4acab79987
sdram/module: cleanup indent
2015-08-20 22:15:06 +02:00
Florent Kermarrec
63538a7d04
litecores: add -Ob option to make.py (allow to build with yosys for example)
2015-08-19 01:17:37 +02:00
Florent Kermarrec
3d3cd128d8
liteeth/phy: only use clk_freq for LiteEthPHYGMIIMII in autodetect
2015-08-19 01:17:35 +02:00
Florent Kermarrec
5253b0c06e
migen/actorlib/packet: fix source.error in Depacketizer
2015-08-19 01:12:07 +02:00
Florent Kermarrec
9210df9e9f
mibuild/xilinx/ise: update synthesis with yosis
2015-08-19 01:12:05 +02:00
Florent Kermarrec
6683485841
tools/flterm: replace int(a, 16) with int(a, 0) for --kernel-adr
2015-08-18 15:47:09 +02:00
Florent Kermarrec
a9d40e790c
tools/flterm.py: cleanup kernel-adr argument parsing
2015-08-13 13:25:02 +02:00
Tim 'mithro' Ansell
d8fd4fe725
Use shutil rather then rm -rf command.
2015-08-13 14:54:58 +08:00
Tim 'mithro' Ansell
eeda704462
Use shell for globbing in clean.
2015-08-13 14:54:58 +08:00
Tim 'mithro' Ansell
d00e774986
All commands run should be checked.
2015-08-13 14:54:58 +08:00
Florent Kermarrec
5a3f4e4179
tools/flterm.py: some cleanup and fix last frame data that was not transmitted
2015-08-12 11:41:08 +02:00
whitequark
abf9a58a3a
unwinder: update.
2015-08-10 16:23:02 +03:00
Florent Kermarrec
646667213e
migen/flow/actor: fix sop/eop validation in PipelinedActor (stb can be inactive when pipe_ce is active)
2015-08-09 19:54:38 +02:00
whitequark
d88904b3d7
libdyld: add const qualifiers.
2015-08-08 15:21:09 +03:00
whitequark
cf3a9e04b8
libbase: add const qualifiers.
2015-08-08 12:16:27 +03:00
whitequark
1b34f48660
libdyld: all ELF relocations may refer to the current object.
2015-08-07 11:05:28 +03:00
Florent Kermarrec
3cf46671e9
liteeth/phy: rename rgmii to s6rgmii since specific to Spartan6
...
Also remove autodetection support for RGMII. For it to work we would need to pass the device we are building for.
2015-08-05 10:33:08 +02:00
Florent Kermarrec
4b8d9b67f3
liteeth: add rgmii phy
2015-08-05 00:50:55 +02:00
Ryan Verner
9c902bcd86
Port fpgalink_programmer to use newer fl library.
...
* See change in 2074e51a33
2015-08-04 21:42:29 +08:00
Florent Kermarrec
c03ef526eb
sdram/phy/s6ddrphy: add DDR3 support
2015-08-04 12:29:42 +02:00
Florent Kermarrec
52fba05e26
sdram/phy/initsequence: add burst chop 4 (BC4) for DDR3
...
This is needed for half rate controllers with burst length of 4.
For best efficiency quarter rate controllers should be used.
2015-08-04 11:19:20 +02:00
whitequark
64f1368938
libunwind: build with -DNDEBUG.
2015-08-02 15:42:02 +03:00
Sebastien Bourdeauducq
b1445ae743
dyld: style
2015-08-02 12:35:48 +08:00
whitequark
6a1b0b342c
libdyld: handle existing but undefined symbols during lookup.
2015-08-02 05:56:11 +03:00
whitequark
36e03ec8a8
libdyld: R_*_RELATIVE never specify a symbol.
2015-08-02 05:29:23 +03:00
whitequark
10773db08d
libdyld: handle unaligned relocations.
2015-08-01 20:26:27 +03:00
whitequark
8a0beb4cfb
unwinder: update.
2015-08-01 20:16:59 +03:00
whitequark
344e1bc6de
libdyld: add support for R_OR1K_{NONE,32,GLOB_DAT}.
2015-08-01 20:16:10 +03:00
whitequark
d625c43591
libbase: also pass exception PC and EA to exception handler.
2015-08-01 20:15:42 +03:00
whitequark
13a50a93d9
libbase: downstream users should provide fprintf.
2015-08-01 20:14:09 +03:00
whitequark
3f7f0a3151
libdyld: fix dyld_lookup algorithm.
2015-08-01 17:21:31 +03:00
whitequark
d43e470e3c
libdyld: fix DT_HASH address calculation.
2015-08-01 15:49:33 +03:00
Sebastien Bourdeauducq
04934ff3f1
software/common.mak: use PYTHON env var
2015-07-31 18:31:04 +08:00
Sebastien Bourdeauducq
df2306ab88
try to use the new anaconda-client
2015-07-31 13:46:28 +08:00