Commit Graph

12 Commits

Author SHA1 Message Date
Tim Paine edbe8294b8 Simplify MANIFEST.in, include files relevant for distribution, add long
description to setup.py, fix classifier tag, tweak CI to start
standardizing workflow
2023-03-21 13:28:32 -04:00
Leon Schuermann 727cc40ab1 Add missing soc/cores/cpu directories to MANIFEST.in 2022-08-09 20:30:04 +02:00
Florent Kermarrec b485829ec4 MANIFEST.in: update. 2021-02-08 10:11:10 +01:00
Arnaud Durand 5e049d8966 Add data dirs to manifest 2020-05-05 22:15:24 +02:00
Tim 'mithro' Ansell 3aee8a5227 Remove directories from submodules from MANIFEST.in file. 2020-04-11 18:37:06 -07:00
Arnaud Durand 68eeba9181
Add verilog submodule from CPU cores to manifest 2019-07-04 00:58:26 +02:00
Florent Kermarrec 17f6cb1f17 initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush) 2016-04-01 00:09:17 +02:00
Florent Kermarrec a775672314 litex: get verilator simulation working and add sim target as example 2015-11-07 23:51:37 +01:00
Florent Kermarrec 6a0f85dc42 litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00
Florent Kermarrec b028569784 import misoc in litex/soc 2015-11-07 12:19:30 +01:00
Sebastien Bourdeauducq 766b0bee65 MANIFEST.in: fix lm32 data directory 2015-10-19 16:30:41 +08:00
Sebastien Bourdeauducq e96eba4493 setup: include software and Verilog files
Broken on Python 3.5
error: can't copy 'misoc/software': doesn't exist or not a regular file
2015-10-05 12:08:02 +08:00