Sebastien Bourdeauducq
|
679d13c99c
|
another attempt at fixing clock routing issues
|
2013-05-06 09:56:10 +02:00 |
|
Sebastien Bourdeauducq
|
7133d9abb0
|
m1crg: reset VGA clock generator
|
2013-03-29 17:14:48 +01:00 |
|
Sebastien Bourdeauducq
|
b603eaf7d4
|
m1crg: allow up to 150MHz pixel clock
|
2013-03-28 20:45:42 +01:00 |
|
Sebastien Bourdeauducq
|
8fd092ca12
|
crg: support VGA pixel clock reprogramming
|
2013-03-28 19:07:17 +01:00 |
|
Sebastien Bourdeauducq
|
0c0140a8fb
|
m1crg: set CLKIN_PERIOD for vga_clock_gen
|
2013-03-17 20:16:58 +01:00 |
|
Sebastien Bourdeauducq
|
70f4c74d46
|
m1crg: advance off-chip DDR clock phase
|
2013-02-24 17:41:56 +01:00 |
|
Sebastien Bourdeauducq
|
7ad2f7081b
|
m1crg: fix signal names
|
2013-02-13 23:59:35 +01:00 |
|
Sebastien Bourdeauducq
|
5649e88a90
|
Use Mibuild
|
2013-02-11 18:23:06 +01:00 |
|
Sebastien Bourdeauducq
|
c86dd3cbef
|
Define clock domains instead of passing extra clocks as regular signals
|
2012-09-11 00:21:07 +02:00 |
|
Sebastien Bourdeauducq
|
3a02524cc7
|
VGA framebuffer connections
|
2012-06-17 13:41:26 +02:00 |
|
Sebastien Bourdeauducq
|
22f7d1716e
|
Remove some boilerplate
|
2012-05-24 19:22:27 +02:00 |
|
Sebastien Bourdeauducq
|
4e18e45686
|
Add Ethernet MAC
|
2012-05-20 00:30:03 +02:00 |
|
Sebastien Bourdeauducq
|
b4e041ecf1
|
s6ddrphy: write path OK in simulation
|
2012-02-20 23:55:20 +01:00 |
|
Sebastien Bourdeauducq
|
f35cd4a85b
|
Prepare for new DDR PHY
|
2012-02-19 18:43:42 +01:00 |
|
Sebastien Bourdeauducq
|
72f9af9d90
|
Generate all clocks for the DDR PHY
|
2012-02-16 18:02:37 +01:00 |