Sebastien Bourdeauducq
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c01594f9fd
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Common interrupt numbers
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2012-05-21 19:52:41 +02:00 |
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Sebastien Bourdeauducq
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94245517f2
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Add timer
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2012-05-21 19:46:04 +02:00 |
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Sebastien Bourdeauducq
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8ad251c94c
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Connect Ethernet IRQ
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2012-05-20 23:48:41 +02:00 |
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Sebastien Bourdeauducq
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4e18e45686
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Add Ethernet MAC
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2012-05-20 00:30:03 +02:00 |
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Sebastien Bourdeauducq
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79124d822b
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Identifier
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2012-05-17 01:41:41 +02:00 |
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Sebastien Bourdeauducq
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141269b384
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Get CSR base addresses from include file
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2012-05-16 10:36:46 +02:00 |
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Sebastien Bourdeauducq
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19b1cc2529
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Remove uses of pads, new constraints system
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2012-04-02 19:22:17 +02:00 |
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Sebastien Bourdeauducq
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c26efa28ca
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asmicon: multiplexer (untested)
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2012-03-18 22:11:01 +01:00 |
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Sebastien Bourdeauducq
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0e00837f42
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asmicon: move slot time to timing settings
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2012-03-18 14:57:31 +01:00 |
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Sebastien Bourdeauducq
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b1eb919ad2
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asmicon: bank machine (untested)
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2012-03-18 00:12:03 +01:00 |
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Sebastien Bourdeauducq
|
7c377880fa
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asmicon: refresher (untested)
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2012-03-15 20:29:26 +01:00 |
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Sebastien Bourdeauducq
|
7b14e0bd05
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asmicon: skeleton
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2012-03-14 18:26:05 +01:00 |
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Sebastien Bourdeauducq
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b4e041ecf1
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s6ddrphy: write path OK in simulation
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2012-02-20 23:55:20 +01:00 |
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Sebastien Bourdeauducq
|
f35cd4a85b
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Prepare for new DDR PHY
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2012-02-19 18:43:42 +01:00 |
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Sebastien Bourdeauducq
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026457a98c
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Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately.
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2012-02-18 18:12:14 +01:00 |
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Sebastien Bourdeauducq
|
5bc840b9c1
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DFI injector (untested)
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2012-02-17 23:50:10 +01:00 |
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Sebastien Bourdeauducq
|
c387ce7ce5
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Map DDR PHY controls in CSR
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2012-02-17 17:34:59 +01:00 |
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Sebastien Bourdeauducq
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5d1dad583b
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Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
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2012-02-17 11:04:44 +01:00 |
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Sebastien Bourdeauducq
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72f9af9d90
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Generate all clocks for the DDR PHY
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2012-02-16 18:02:37 +01:00 |
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Sebastien Bourdeauducq
|
5165ff7ec3
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Include Wishbone to ASMI bridge
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2012-02-13 23:12:57 +01:00 |
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Sebastien Bourdeauducq
|
58f4f78d2c
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sram: fix sub-word write
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2012-02-06 23:13:35 +01:00 |
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Sebastien Bourdeauducq
|
33f1c456bf
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top: connect UART IRQ
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2012-02-06 17:45:40 +01:00 |
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Sebastien Bourdeauducq
|
9b9a510525
|
Memory map
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2012-02-05 19:54:08 +01:00 |
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Sebastien Bourdeauducq
|
28f00c3a9a
|
Add on-chip SRAM
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2012-01-27 22:09:03 +01:00 |
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Sebastien Bourdeauducq
|
6fde54c5aa
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Use meaningful class names
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2012-01-21 12:25:22 +01:00 |
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Sebastien Bourdeauducq
|
f6aa95a4d0
|
Use new verilog.convert API
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2012-01-20 23:00:11 +01:00 |
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Sebastien Bourdeauducq
|
570ea8ccf8
|
convtools -> tools
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2012-01-13 17:07:46 +01:00 |
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Sebastien Bourdeauducq
|
b60abfaa4a
|
Convert -> convert
|
2012-01-05 19:27:45 +01:00 |
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Sebastien Bourdeauducq
|
6664af73d1
|
uart: new design using FHDL and bank (TX only, incomplete)
|
2011-12-18 00:29:37 +01:00 |
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Sebastien Bourdeauducq
|
0e30d67fa3
|
Multiply system clock
|
2011-12-17 15:00:18 +01:00 |
|
Sebastien Bourdeauducq
|
411e1af980
|
Proper reset generation
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2011-12-16 22:25:26 +01:00 |
|
Sebastien Bourdeauducq
|
ca68097ef6
|
Pay a bit more attention to PEP8
|
2011-12-16 16:02:49 +01:00 |
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Sebastien Bourdeauducq
|
b487e99bcf
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Initial import
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2011-12-13 17:33:12 +01:00 |