Sebastien Bourdeauducq
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b4e041ecf1
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s6ddrphy: write path OK in simulation
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2012-02-20 23:55:20 +01:00 |
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Sebastien Bourdeauducq
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ce51653381
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s6ddrphy: generate DQ/DQS/DM OE
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2012-02-20 16:13:56 +01:00 |
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Sebastien Bourdeauducq
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cbc3b7fa83
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s6ddrphy: DQ/DQS/DM SERDES
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2012-02-20 13:45:57 +01:00 |
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Sebastien Bourdeauducq
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4c1e18a9b5
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s6ddrphy: clock, address and command
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2012-02-19 20:49:56 +01:00 |
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Sebastien Bourdeauducq
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f35cd4a85b
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Prepare for new DDR PHY
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2012-02-19 18:43:42 +01:00 |
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Sebastien Bourdeauducq
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cdd58e023b
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s6ddrphy: use single-ended DQS
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2012-02-17 10:53:58 +01:00 |
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Sebastien Bourdeauducq
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72f9af9d90
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Generate all clocks for the DDR PHY
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2012-02-16 18:02:37 +01:00 |
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Sebastien Bourdeauducq
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1368b666df
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s6ddrphy: prepare quilt
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2012-02-14 15:52:39 +01:00 |
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Sebastien Bourdeauducq
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b6b1901bb8
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LM32: make IP read-only and interrupt lines level-sensitive
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2012-02-07 00:07:12 +01:00 |
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Sebastien Bourdeauducq
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6664af73d1
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uart: new design using FHDL and bank (TX only, incomplete)
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2011-12-18 00:29:37 +01:00 |
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Sebastien Bourdeauducq
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bb21f7584a
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32-device, 8-bit CSR bus
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2011-12-17 15:54:42 +01:00 |
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Sebastien Bourdeauducq
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411e1af980
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Proper reset generation
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2011-12-16 22:25:26 +01:00 |
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Sebastien Bourdeauducq
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b487e99bcf
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Initial import
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2011-12-13 17:33:12 +01:00 |