Commit Graph

26 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 679d13c99c another attempt at fixing clock routing issues 2013-05-06 09:56:10 +02:00
Sebastien Bourdeauducq 784e96bb87 build.py: LOC clock generator components to limit breakage of the ISE shitware 2013-05-05 23:07:15 +02:00
Sebastien Bourdeauducq 11cbdf0d4f build.py: support single DVI sampler 2013-05-05 20:56:58 +02:00
Sebastien Bourdeauducq 53e5c4f59c build: only add UCF constraints for the cores that are present 2013-05-02 23:56:09 +02:00
Sebastien Bourdeauducq de76faf757 Tell the Xilinx crapware that DCM_CLKGEN does not phase align, as some (but not all) of the ISE tools remark. 2013-04-25 20:18:45 +02:00
Sebastien Bourdeauducq 4ff1175dcf Use the Migen asynchronous FIFO 2013-04-25 19:43:26 +02:00
Sebastien Bourdeauducq 1e860c7472 Use new Mibuild generic_platform API 2013-03-26 17:57:17 +01:00
Sebastien Bourdeauducq fdf7f10f54 Automatically build CSR access functions 2013-03-25 14:42:48 +01:00
Sebastien Bourdeauducq 0a14c3714b dvisampler: software controlled phase detector 2013-03-21 00:46:29 +01:00
Sebastien Bourdeauducq 9f02ced39e dvisampler: add clocking and phase detector 2013-03-17 14:43:10 +01:00
Sebastien Bourdeauducq b2173bba9f Use new ClockDomain API 2013-03-15 19:17:05 +01:00
Sebastien Bourdeauducq eaef3464e9 Instantiate DVI sampler core for both ports 2013-03-13 19:56:56 +01:00
Sebastien Bourdeauducq 1e7783a41e build.py: use implicit get_fragment 2013-03-12 16:13:20 +01:00
Sebastien Bourdeauducq b854f1ad32 build: support optional MMU 2013-02-24 16:28:59 +01:00
Sebastien Bourdeauducq 43343b131f lm32: use submodule 2013-02-24 15:57:19 +01:00
Sebastien Bourdeauducq 5649e88a90 Use Mibuild 2013-02-11 18:23:06 +01:00
Sebastien Bourdeauducq 4e18e45686 Add Ethernet MAC 2012-05-20 00:30:03 +02:00
Sebastien Bourdeauducq 48ddbf0c85 Add build Makefile and JTAG load script 2012-02-17 18:09:48 +01:00
Sebastien Bourdeauducq 5d1dad583b Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
2012-02-17 11:04:44 +01:00
Sebastien Bourdeauducq 72f9af9d90 Generate all clocks for the DDR PHY 2012-02-16 18:02:37 +01:00
Sebastien Bourdeauducq aef2e4b5e8 Use double quotes for all strings 2012-02-14 13:15:00 +01:00
Sebastien Bourdeauducq b60abfaa4a Convert -> convert 2012-01-05 19:27:45 +01:00
Sebastien Bourdeauducq 6664af73d1 uart: new design using FHDL and bank (TX only, incomplete) 2011-12-18 00:29:37 +01:00
Sebastien Bourdeauducq 411e1af980 Proper reset generation 2011-12-16 22:25:26 +01:00
Sebastien Bourdeauducq ca68097ef6 Pay a bit more attention to PEP8 2011-12-16 16:02:49 +01:00
Sebastien Bourdeauducq b487e99bcf Initial import 2011-12-13 17:33:12 +01:00