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8070 Commits

Author SHA1 Message Date
Ilia Sergachev f8863bb986 integration/soc: cleanup formatting and comments 2022-01-15 17:12:31 +01:00
Ilia Sergachev 0e87b9b9be integration/builder: print missing key name 2022-01-15 17:09:11 +01:00
Stafford Horne 5992e1db8c marocchino: Add initial support for new OpenRISC core 
The Marocchino is a superscaler OpenRISC implementation which has
advanced features including 64-bit double FPU support.

Much of the python module here is copied form mor1kx like the *.S
and *.h files.
 2022-01-15 07:30:46 +09:00
Gabriel Somlo c3b94a347e cpu/rocket: increase IRQ lines to 8 2022-01-14 17:08:15 -05:00
Florent Kermarrec cdacba06d1 soc/add_spi_sdcard: Fix missing renaming when rst pin is present. 2022-01-14 19:16:31 +01:00
enjoy-digital ffc96a5655
Merge pull request #1155 from tongchen126/master 
litex/soc/software/bios/cmds/cmd_mem.c: add mem_cmp
 2022-01-14 19:02:16 +01:00
Florent Kermarrec 96a9495d6a soc/add_spi_sdcard: Add optional Tristate. 
This is required on some boards where the SDCard is shared with other chips (ex ESP32 on ULX3S).
 2022-01-14 15:01:13 +01:00
enjoy-digital 4475b978d5
Merge pull request #1159 from fjullien/fix_cmd_mem_write 
bios: fix mem_write address increment
 2022-01-14 13:53:41 +01:00
Franck Jullien 8f1d50525d bios: fix mem_write address increment 2022-01-14 13:16:02 +01:00
tongchen126 1b9bdc57ac litex/soc/software/bios/cmds/cmd_mem.c: add mem_cmp 2022-01-12 12:09:00 +08:00
Florent Kermarrec add2746a54 tools/litex_cli: Rename wb to bus. 2022-01-11 14:54:18 +01:00
Florent Kermarrec a8de9054a3 tools/litex_client: Allow passing CSR name to --read/--write to simplify use. 
ex:
litex_cli --read ctrl_scratch
litex_cli --write ctrl_scratch 0x5aa55aa5
 2022-01-11 14:53:09 +01:00
Franck Jullien 438bb0b570 sim: allow custom modules to be in custom path 
If a project needs a custom verilator module, it can now
specifies the path where the module's directory is.

SimPlatform can now look for extra modules:

    builder.build(
        extra_mods = ["mymodule1", "mymodule2"],
        extra_mods_path = os.path.abspath(os.getcwd()) + "/modules",
        sim_config=sim_config
    )

Modules must be subdirectories of extra_mods_path:

.
├── modules
│   ├── mymodule1
│   ├── mymodule2
│   ├── ...
 2022-01-09 21:15:11 +01:00
Florent Kermarrec a330e9fda5 cores/spi_flash: Deprecate SPI Flash MMAPed cores (Designs have been switched with LiteSPI). 2022-01-07 19:08:03 +01:00
Florent Kermarrec 30a99582ae litex/compat: Fully deprecate up5kspram renaming. (Warning to suggest change has been here for > 1 year). 2022-01-07 18:40:12 +01:00
Florent Kermarrec c46824153d litex/compat: Fully deprecate soc_sdram (Warning to suggest change has been here for > 1 year). 2022-01-07 18:38:56 +01:00
Florent Kermarrec c010a98719 cpu: Add default set_reset_address function to CPU that will be overrided by each CPU (avoid hasattr check). 2022-01-07 15:17:37 +01:00
Florent Kermarrec cb13f71b56 build/openocd/stream: Add get_ir method and use it to compute IR and handle specific ECP5 case. 
JTAG-UART/JTAGBone on ECP5 non longer requires --jtag-chain=49 command.
 2022-01-07 11:39:05 +01:00
Florent Kermarrec f404877353 soc/SoCBusHandler: Add io_regions_check attribute and and disable IO region check with CPUNone. 2022-01-07 10:47:47 +01:00
Florent Kermarrec e0961d7cb1 cores/cpu: Add missing Gowin EMCU comment. 2022-01-07 10:46:58 +01:00
Florent Kermarrec 23214638e4 cores/cpu: Allow multiple calls to set_reset_address (= override) since reset_adress is not not necessarily known at SoC creation. 
When booting from SPI Flash, things will be done in the following order:
- SoC creation.
- SPI Flash peripheral creation (with dynamic mapping).
- CPU reset address can then be set.
 2022-01-07 09:07:34 +01:00
Florent Kermarrec 5c278ae437 cpu/rocket/core: Move IO Region (ROM/SRAM can't be in an IO Region). 2022-01-06 15:32:31 +01:00
Florent Kermarrec 23b9d73354 integration/soc: Improve mem_map overriding display. 2022-01-06 13:46:21 +01:00
enjoy-digital 5363d61859
Merge pull request #1151 from fjullien/fix_wb_slave_cache_configuration 
soc: raise an error if adding a SoCRegion with incoherent cache configuration
 2022-01-06 10:12:20 +01:00
Franck Jullien 330144021b soc: raise an error if adding a SoCRegion with incoherent cache configuration 2022-01-06 09:55:53 +01:00
Florent Kermarrec 153f9e9f6c integration/builder: Use custom Formatter settings to improve readibility and minor cleanups. 2022-01-05 19:23:06 +01:00
Florent Kermarrec 1279ebebe8 build: Create toolchain parser group to improve --help readibility and cleanup. 2022-01-05 18:53:43 +01:00
Florent Kermarrec 0c1f0b17b4 integration/soc_core: Create soc parser group to improve --help readibility. 2022-01-05 18:30:04 +01:00
Florent Kermarrec ec75228a72 builder: Create builder parser group to improve --help readibility. 2022-01-05 18:29:38 +01:00
Florent Kermarrec 67fa433efa tools: Switch most the tools to argparse.ArgumentDefaultsHelpFormatter and uniformize help style. 2022-01-05 16:04:31 +01:00
Florent Kermarrec 54a137ef9f builder: Use argparse.ArgumentDefaultHelpFormatter to automatically show default in help. 2022-01-05 16:03:38 +01:00
Florent Kermarrec 6f3f695d61 tools/litex_sim: Minor cleanups. 2022-01-05 15:20:27 +01:00
Florent Kermarrec c424e51df4 litex_setup: Improve script status prints. 2022-01-05 14:52:21 +01:00
Florent Kermarrec a6e2a529dc litex_setup: Add initial installs config support (minimal, standard, full). 
Can be selected with --config=minimal/standard/full. This avoid installing all the
CPUs when only the popular ones will be used. Installation can be updated later
and switched to full installation with --config=full.
 2022-01-05 13:56:35 +01:00
Florent Kermarrec 04e73b2e33 litex_setup.py: Switch git clone to git@github.com URLs when in --dev mode. 
Simplify dev/maintenance.
 2022-01-05 10:07:35 +01:00
Florent Kermarrec ba79224939 Bump year. 2022-01-05 09:21:08 +01:00
Florent Kermarrec 3fde251216 CHANGES: Set release date. 2022-01-05 08:53:10 +01:00
Florent Kermarrec e21044641e cores/cpu/vexriscv_smp: Force wishbone_memory mode when no direct memory_buses. 
This ensures a path for memory accesses will be created LiteDRAM is not used (ex with an HyperRAM memory).
 2022-01-04 15:16:31 +01:00
Florent Kermarrec f04a3dcc50 CHANGES: List changes since 2021.08. 2022-01-03 19:29:05 +01:00
enjoy-digital c6dff1ea7e
Merge pull request #1141 from sergachev/zynq7000_bios 
Zynq7000 ARM BIOS support
 2022-01-03 17:57:40 +01:00
enjoy-digital 3b05fa57d4
Merge pull request #1140 from sergachev/cleanup_defaults 
argparse: deduplicate defaults in help messages
 2022-01-03 14:59:19 +01:00
Florent Kermarrec 79d0f0a893 interconnect/wishbone/axi: Automatically get InterconnectShared's shared data_width from first master. 2022-01-03 14:53:06 +01:00
enjoy-digital 90c204e87f
Merge pull request #1148 from tongchen126/master 
soc/software/bios/cmds/cmd_mem.c: fix number of required params
 2022-01-03 14:40:39 +01:00
tongchen126 a8c8e4e3cf litex/soc/interconnect/wishbone.py: add data_width param 2021-12-31 13:27:27 +08:00
tongchen126 e87e7ff31c soc/software/bios/cmds/cmd_mem.c: fix number of required params 2021-12-30 20:43:05 +08:00
Florent Kermarrec 8ac3fbc039 soc/cores/led: Split LED-SHIFT in LED-READ/LED-SHIFT, simplify and fix off by one error. 2021-12-27 14:06:04 +01:00
enjoy-digital 2c68135eb4
Merge pull request #1143 from enjoy-digital/Dolu1990-patch-1 
tools/litex_json2dts_linux.py fix double {{
 2021-12-27 12:34:19 +01:00
Dolu1990 f4967cfb85
tools/litex_json2dts_linux.py fix double {{ 
A string with a {{ was missing the .format call, generating some broken dts
 2021-12-26 12:17:33 +01:00
Ilia Sergachev 6b207f876b software/bios: add separate linker file for zynq 2021-12-22 03:01:25 +01:00
Ilia Sergachev d75dd653bc integration/soc: unblacklist zynq 2021-12-22 03:01:06 +01:00