587e09e3d6
software/liblitesdcard: increase sdcard_wait_cmd_done/sdcard_wait_data_done busy_wait.
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Required after the command refactoring, will need to be adjusted.
2020-08-27 12:52:11 +02:00
4025257d8d
software/liblitesdcard/sdcard: cleanup, update copyrights.
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- improve indent.
- remove do/while in block functions (block's length/count only need to be configured once).
- update copyrights.
2020-08-27 12:36:35 +02:00
334635a97f
software/liblitesdcard: remove wait for DMA Reader to complete, fix ifdef on SDCARD_CMD23_SUPPORT.
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The FIFO after the DMA has been reduced and is no longer able to store an entire block, so the DMA will not complete
if write is not released.
2020-08-26 12:47:50 +02:00
4ac0ed49e1
software/liblitesdcard/bios: add sdfreq command to configure SDCard clock frequency.
2020-08-26 12:43:09 +02:00
3897acb9e4
lattice/nx: update copyrights.
2020-08-24 22:32:49 +02:00
4364043b08
integration/soc: expose integrated_rom_mode to allow ROM to be writable (useful for BIOS/ROM development where content is reloaded over UARTBone/Etherbone).
2020-08-24 18:19:03 +02:00
885c339d97
soc/cores: add initial NX-LRAM support.
2020-08-24 16:24:34 +02:00
cf13833e3c
cores/clock: add initial NX-OSCA support.
2020-08-24 16:23:27 +02:00
e441bd60fa
build/lattice: add initial Radiant support for NX FPGA family (Crosslink-NX/Certus-NX).
2020-08-24 16:23:22 +02:00
8a44464a45
Merge pull request #640 from antmicro/mor1kx_dt
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litex_json2dts: Add support for mor1kx
2020-08-24 14:26:11 +02:00
4f1c32abdc
targets/de0nano: set sys2x_ps to 180° for sdram_rate=1:2.
2020-08-24 09:30:38 +02:00
d16051ff90
boards/ulx3s: keep up to date with litex-boards.
2020-08-24 09:08:30 +02:00
d826c60658
soc/cores/clock/ECP5PLL: specificy CLKOS3_F/CPHASE and -1 on cphase to match Clarity Designer values.
2020-08-24 09:04:33 +02:00
9e37b16ec0
soc/interconnect/axi/AXILite2CSR: add register parameter for genericity.
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Not yet used, but simplify SoC integration.
2020-08-24 09:03:04 +02:00
4dab1eb0c8
litex_json2dts: Add support for mor1kx
2020-08-24 08:02:16 +02:00
42d8fc226a
Merge branch 'master' of https://github.com/enjoy-digital/litex
2020-08-23 15:42:39 +02:00
77ae243310
test: add SPDX License identifier to header and specify file is part of LiteX.
2020-08-23 15:40:21 +02:00
b8371ef480
tools: add SPDX License identifier to header and specify file is part of LiteX.
2020-08-23 15:37:16 +02:00
93d906f9d1
soc: add SPDX License identifier and specify file is part of LiteX.
2020-08-23 15:33:01 +02:00
e52ffd2da0
gen: add specify SPDX License identifier and specify file is part of Migen and has been modified/adapted for LiteX.
2020-08-23 15:19:46 +02:00
70610b2332
build: add SPDX License identifier and specify file is part of LiteX.
2020-08-23 15:14:45 +02:00
6ee882d1ec
platforms/targets: add SPDX License identifier to header and specify file is part of LiteX.
2020-08-23 15:08:15 +02:00
ee0e240242
Merge pull request #631 from gsomlo/gls-abc9-fixup
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build/lattice/trellis: make "-abc9" an optional argument
2020-08-22 20:06:57 +02:00
9950e75654
build/io: fix InferedSDRIO (thanks @mtdudek).
2020-08-22 19:49:34 +02:00
bae871a884
Merge pull request #632 from gsomlo/gls-sdcard-refactor
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refactor sdcard (bios) software
2020-08-22 19:44:59 +02:00
3206dba911
Merge pull request #636 from Xiretza/minerva-cli-filetype
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Fix call to generation of minerva output file
2020-08-22 19:41:07 +02:00
8bc5dd7c8c
Merge pull request #635 from Xiretza/collections-abc-deprecation
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Fix DeprecationWarning for collections.abc
2020-08-22 19:40:44 +02:00
7984436248
Merge pull request #634 from betrusted-io/spi_opi_timing_only
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add a pipe register to relax an async_default timing path
2020-08-22 19:39:51 +02:00
e3bb3a9488
Fix call to generation of minerva output file
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With nmigen/nmigen#a7b8ced, cli.py no longer defaults to generating
verilog code, so -t/--type has to be specified explicitly.
$ pytest test/test_targets.py -k test_variants_minerva
[...]
cli.py: error: specify file type explicitly with -t
2020-08-22 14:54:40 +02:00
fcc7058bfc
Fix DeprecationWarning for collections.abc
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DeprecationWarning: Using or importing the ABCs from 'collections' instead of from 'collections.abc' is deprecated since Python 3.3, and in 3.9 it will stop working
2020-08-22 13:39:30 +02:00
d783e86ff6
add a pipe register to relax an async_default timing path
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there is an async reset signal going to a FIFO
that can't be false_path'd because its timing is important
to making sure that the burst FIFO is reset to zero when
a miss happens in the burst cache. Unfortunately as designs
get full, the routability of this signal becomes difficult
and drives up the compile time and reduces quality of results.
There is enough time in the design to insert a single pipe stage
to alleviate the timing somewhat. This commit adds that register.
2020-08-20 04:14:10 +08:00
e0b2b8153f
liblitesdcard/sdcard: read sdcard response only when needed
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Instead of reading the 128 byte sdcard response after each operation,
read it only during debugging and/or when it's necessary (to retrieve
the relative card address, rca).
We no longer need a global sdcard_response array, and refactor the
various retrieval and reporting functions to contain a local buffer
for that purpose, only if/when necessary.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-08-17 18:45:24 -04:00
a47b2de5fe
sdcard: refactor command functions
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Factor out common portion of command functions. Also use appropriate
unsigned int width (e.g., uint16_t) for arguments.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-08-17 18:45:24 -04:00
bfd6b3c3f4
liblitesdcard/sdcard: cosmetic fixes (indentation, #ifdef, etc.)
2020-08-17 18:45:24 -04:00
37ebcd3be7
factor out busy_wait_us()
2020-08-17 18:45:24 -04:00
c4710b371a
build/lattice/trellis: make "-abc9" an optional argument
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Fix up earlier commit (#6c298cb7) and make the '-abc9' optional
argument to yosys' synth_ecp5 actually optional (and off by default)
in LiteX's trellis build infrastructure.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-08-15 16:49:08 -04:00
35929c0f8a
soc/integration/csr_bridge: use registered version only when SDRAM is present.
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Seems to be a good compromise for now.
2020-08-14 15:29:49 +02:00
e4f5dd987e
interconnect/wishbone/Wishbone2CSR: add registered version and use it as default.
2020-08-14 00:47:05 +02:00
b344196aba
build/lattice/diamond: use diamondc instead of pnmainc (avoid having to set environment variables).
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http://www.latticesemi.com/en/Support/AnswerDatabase/5/5/2/5522
2020-08-14 00:10:56 +02:00
f730f1d7ba
cores/cpu/vexriscv_smp fix argument parsing
2020-08-13 12:52:05 +02:00
0e480dd662
bios/main/sdram: fix speed reporting (Mbps/pin not MHz).
2020-08-11 22:13:14 +02:00
bb7f33434e
Merge pull request #627 from gsomlo/gls-dma-addr-64
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RFC: cores/dma, liblitesdcard/sdcard: use 64 bits for dma base address
2020-08-10 21:44:02 +02:00
ba34c85284
cores/dma, liblitesdcard/sdcard: use 64 bits for dma base address
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Make the DMA base address register 64-bit wide, to cover situations
in which the physical memory being accessed is above the 4GB limit
(e.g., on 64-bit systems with more than 4GB of provisioned physical
memory).
Also update DMA reader/writer setup call sites in the bios (currently
only used by litesdcard).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-08-10 14:09:25 -04:00
4cf28a0107
software/bios: display SDRAM databits and freq.
2020-08-07 19:49:02 +02:00
6f69679d21
cpu/vexriscv_smp: more coherent_dma to __init__ instead of add_memory_buses.
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LiteX is creating the SoC.dma_bus just after the CPU is declared, so declaring it in add_memory_buses was preventing it.
It's also more coherent to move it to __init__ since not related to the memory_buses.
2020-08-07 14:47:21 +02:00
b3531cd2a8
cores/cpu: add external cpu_type.
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Allows fully pluggable CPUs where cpu_type is set to "external" and cpu_cls provided externally.
2020-08-07 11:16:00 +02:00
b9d3aab59d
targets: use platform.request_all on LedChaser.
2020-08-06 20:02:17 +02:00
14c9166429
build/generic_platform: add request_all method.
2020-08-06 20:00:07 +02:00
57335b9971
cores/cpu/zynq7000: simplify using new loose parameter of Platform.request.
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And avoid the try/except that can mask others errors.
2020-08-06 19:44:46 +02:00
4867f2b324
Merge pull request #624 from trabucayre/emio_zynq
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soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode
2020-08-06 19:34:03 +02:00
Florent Kermarrec
Piense
Mateusz Holenko
Xiretza
bunnie
Gabriel Somlo
Dolu1990