Commit Graph

8224 Commits

Author SHA1 Message Date
Florent Kermarrec 7ebc7625d5 tools/litex_client: Add --csr-csv support.
Useful to debug multi-FPGA projects.
2022-03-07 11:42:32 +01:00
Florent Kermarrec 87d5d7c87c cpu/firev/core: Review/Cleanup pass, also fix set_reset_address. 2022-03-04 12:12:06 +01:00
enjoy-digital ea883909b5
Merge pull request #1232 from sylefeb/silice-firev
Silice FireV
2022-03-04 11:41:13 +01:00
Florent Kermarrec 8ade60a55d soc/reset: Change the way crg_rst is set to allow possible multiple assignation in the code.
This allows user's cores to also exercise the CRG rst with code similar to:
self.comb += If(<rst_condition>, self.crg.rst.eq(1))
2022-03-04 10:47:52 +01:00
sylefeb 2d40846c34
Merge branch 'enjoy-digital:master' into silice-firev 2022-03-03 21:41:21 +01:00
enjoy-digital 7fcecf437a
Merge pull request #1230 from antmicro/add-cpus-to-litex_json2renode
Add CPUs to litex_json2renode script
2022-03-03 17:33:43 +01:00
Florent Kermarrec b092d2a180 cores/jtag: Fix chain parameter on XilinxJTAG. 2022-03-03 16:45:20 +01:00
Florent Kermarrec e00eafd97f cores/ram: Add Xilinx Ultrascale+ HBM2 wrapper. 2022-03-03 16:33:05 +01:00
Sylvain Lefebvre f5f0937493 added firev CPU 2022-03-03 15:07:38 +01:00
Michal Sieron c3fb321532 tools/litex_json2renode: Add support for Minerva 2022-03-03 12:04:33 +01:00
Michal Sieron d86bdb71ec tools/litex_json2renode: Don't use generic RV32 for Ibex 2022-03-03 12:03:03 +01:00
Michal Sieron 35dd5554ba tools/litex_json2renode: Add cv32e40p support 2022-03-03 11:59:26 +01:00
enjoy-digital 46361db135
Merge pull request #1229 from smunaut/jtag-zynq-usp
cores/jtag/XilinxJTAG: Add support for Zynq UltraScale+
2022-03-02 21:56:03 +01:00
Sylvain Munaut d8df6cb27d cores/jtag/XilinxJTAG: Add support for Zynq UltraScale+
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-03-02 14:12:18 +01:00
Florent Kermarrec 4bc1691487 soc/cores/xadc: Update copyrights. 2022-03-01 14:48:02 +01:00
Florent Kermarrec 0a40616df9 litex_setup.py: Remove LiteHyperBus dependency (not currently used by LiteX-Boards).
We could add it back as a dependency if the simple/portable core is no longer enough for
regular use cases.
2022-03-01 09:27:23 +01:00
Florent Kermarrec dbde036162 soc/cores: Re-integrated generic/portable HyperBus/HyperRAM core from LiteHyperBus.
The generic version of the HyperRAM core is simple enough to be directly integrated in LiteX
which avoid an additional dependency.
2022-03-01 09:11:55 +01:00
enjoy-digital 6c93db0f14
Merge pull request #1228 from sergachev/master
Minor fixes
2022-02-28 11:01:02 +01:00
Ilia Sergachev 6e87827ce2 integration/soc: fix inexistent word "supporteds" 2022-02-26 10:41:14 +01:00
Ilia Sergachev 54bed133f4 build/tools: add .vp encrypted verilog file extension awareness 2022-02-26 10:38:11 +01:00
Florent Kermarrec 7f49c5235e core/video: Update copyrights. 2022-02-25 11:28:09 +01:00
enjoy-digital 89f19ea510
Merge pull request #1226 from smunaut/sysmon
cores/xadc: Improve support for Zynq Ultrascale+
2022-02-25 10:39:40 +01:00
enjoy-digital 22886f3465
Merge pull request #1227 from fjullien/fix_video
Fix video (vtg and colorbars)
2022-02-25 10:38:46 +01:00
Franck Jullien a916a1df24 video:ColorBars: fix for hres not divisible by 8 2022-02-25 09:26:22 +01:00
Franck Jullien ced763e3d9 video:vtg: fix off by one error in hscan and vscan 2022-02-25 09:26:22 +01:00
Sylvain Munaut 8f00b0f182 cores/xadc: Improve support for Zynq Ultrascale+
Although for 'standard' UltraScale+ just letting Vivado upgrade
SYSMONE1 to SYSMONE4 works, it doesn't for the Zynq because the
default SIM_DEVICE not matching up creates a fatal DRC when
creating bitstream.

So instead we add separate classes for UltraScale, UltraScale+ and
Zynq UltraScale+, each instanciating the right blocks, with the
right params. Also we only create the VCCPSINTLP//VCCPSINTFP/VCCPSAUX
for the Zynq UltraScale+.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-02-25 09:21:19 +01:00
enjoy-digital b54384ca73
Merge pull request #1225 from fjullien/efinix_dbparser
efinix:dbparser: add get_pad_name_from_pin and use it
2022-02-24 22:29:54 +01:00
enjoy-digital 8303e462ec
Merge pull request #1224 from fjullien/fix_add_sources
platform: fix add_sources
2022-02-24 22:29:18 +01:00
enjoy-digital b77fb9f6a1
Merge pull request #1223 from fjullien/efinix_add_mipi_tx_block
efinix: add MIPI TX block
2022-02-24 22:27:51 +01:00
enjoy-digital 97d1ae0fc2
Merge pull request #1222 from fjullien/efinix_implement_fix_xml
efinix: add a list of values to fix in xml
2022-02-24 22:26:23 +01:00
enjoy-digital 9c01eff5fa
Merge pull request #1221 from fjullien/efinix_implement_phase_shift_pll_v3
efinix: implement pll v3 phase shift
2022-02-24 22:24:31 +01:00
Franck Jullien e15cd66762 efinix: implement pll v3 phase shift 2022-02-24 21:40:53 +01:00
Franck Jullien 1b22c6c0ad efinix: add a list of values to fix in xml
Sometimes the Python API of the interface designer produce a wrong XML
file. Values can be changed in the XML file with this new list.
For example:

fix_pll = [
	#      Tag              name                    properties / values
	("comp_output_clock", "mipi_clk",             [("out_divider", "20")]),
        ("comp_output_clock", "mipi_tx_clk_fastclk",  [("out_divider", "4"), ("phase_setting", "3")]),
        ("comp_output_clock", "mipi_tx_data_fastclk", [("out_divider", "4"), ("phase_setting", "1")]),
        ("comp_output_clock", "mipi_tx_slowclk",      [("out_divider", "16")])
]

platform.toolchain.ifacewriter.fix_xml += fix_pll
2022-02-24 21:40:17 +01:00
Franck Jullien 77e55978d8 efinix: add MIPI TX block 2022-02-24 21:38:26 +01:00
Franck Jullien 289c7fbf54 platform: fix add_sources
If the Builder class is not used to build the projet, platform sources
is still a list of tupples with 4 elements.

For now, we don't handle file copy when Builder is not used but at least
it won't crash.
2022-02-24 21:24:05 +01:00
Franck Jullien 9de86c84d6 efinix:dbparser: add get_pad_name_from_pin and use it
get_gpio_instance_from_pin returned the pad name.
It now returns the gpio block name.

To get the pad name, there is now get_pad_name_from_pin.
2022-02-24 21:11:40 +01:00
Florent Kermarrec f6d6611a81 software/liblitedram: Introduce SDRAM_PHY_DELAY_JUMP and set to 4 on 7-Series instead of 1 to improve calibration robustness on some boards.
This is for example required on the STLV7325 board.
2022-02-24 17:32:58 +01:00
Florent Kermarrec 82daa48e09 software/bios/libbase: Always do memtest/memspeed when main_ram is present.
- Enable memtest/memspeed on design with HyperRAM.
- Allow comparisons between SDRAM/HyperRAM and integrated RAM.
2022-02-23 10:19:20 +01:00
Dolu1990 4acbafbc19 cpu/naxriscv allow reset_vector >= 0x80000000 2022-02-22 12:21:05 +01:00
Dolu1990 038b66bae5 cpu/naxriscv add reset vector support 2022-02-22 11:06:02 +01:00
Dolu1990 cd57202e5e
cpu/NaxRiscv fix for windows 2022-02-22 10:37:22 +01:00
Florent Kermarrec 1b62f14230 build: Add initial OpenFPGA build backend with SOFA support and minimal blinky example.
OpenFPGA should be installed by following installation steps from https://github.com/lnis-uofu/OpenFPGA.
SOFA can be cloned from https://github.com/lnis-uofu/SOFA

Environment variables then need to be set:
export LITEX_ENV_OPENFPGA=/PATH_TO_OPENFPGA
export LITEX_ENV_OPENFPGA_SOFA=/PATH_TO_SOFA

A simple blinky test design is provided and can be built by executing blinky.py.
2022-02-21 17:07:39 +01:00
Florent Kermarrec 8559b88ad8 build/efinix/platform: Transform Slices until we get target Signal (fixes SDCard SD-mode on TI62-F225). 2022-02-21 10:34:09 +01:00
Dolu1990 d2a2c2e5dc
cpu/naxriscv update nax
fix sbt version
2022-02-20 22:31:04 +01:00
enjoy-digital 9d68a9479c
Merge pull request #1153 from fjullien/allow_module_in_project_dir
sim: allow custom modules to be in custom path
2022-02-18 17:16:25 +01:00
enjoy-digital fde7fc87a3
Merge pull request #1214 from Dolu1990/memspeed
Improve bios memspeed performances
2022-02-18 16:30:30 +01:00
Dolu1990 ea6cadf7b2 bios/memtest fix tabulations 2022-02-18 13:23:10 +01:00
Dolu1990 eccd64348d bios/memtest improve memspeed performances 2022-02-18 13:21:05 +01:00
Florent Kermarrec 3510daaf0c clock/efinix/create_clkout: Set with_reset to True by default (similar to others vendors). 2022-02-18 12:10:43 +01:00
Dolu1990 6049018f10 cpu/naxriscv fix boot-helper.S 2022-02-18 11:54:47 +01:00