af0dc7f98b
Merge pull request #2055 from trabucayre/gowin_apicula_fix
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Gowin apicula fix
2024-09-02 14:08:07 +02:00
babe233407
build/gowin/apicula: only append _packer_opts with known use_xxx (drop options only required by Gowin's software)
2024-09-01 09:55:01 +02:00
3da470048a
build/gowin/apicula: append _synth_opts with specific requirements according to FPGA model
2024-09-01 09:53:24 +02:00
2f2b292e06
vexii add with-cpu-clk
2024-08-30 18:16:56 +02:00
15cd556750
Merge pull request #2053 from enjoy-digital/hyperram_new
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soc/cores/hyperbus: Full rewrite of HyperRAM core.
2024-08-30 15:38:59 +02:00
61b54aa491
soc/integration/soc: Fix add_peripheral.
2024-08-30 12:08:00 +02:00
c554752e8a
soc/cores/hyperbus: Add automatic read burst detection.
2024-08-30 11:53:14 +02:00
c14f1d0816
vexiiriscv add video support
2024-08-30 10:44:36 +02:00
5fb873d209
efinix: Add support for more IO
2024-08-30 10:44:10 +02:00
3bde3e9848
soc/cores/hyperbus: Add automatic write burst detection.
2024-08-29 19:20:23 +02:00
fac80c3a51
soc/cores/hyperbus: Full rewrite of HyperRAM core.
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Rewriting the HyperRAM core to improve its design and functionality. The
old core grew complex over time without a clear structure. This new version
offers:
- IO registers on all signals for better performance.
- Flexible clocking options.
- Simplified architecture.
- Easier to extend with new features.
This rewrite provides a base for future development.
2024-08-29 12:54:09 +02:00
cc3f13670a
Merge pull request #2050 from Dolu1990/efinix_pll_ext_fix
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efinix: Fix PLL with external clock input ifacewriter
2024-08-28 20:13:03 +02:00
d4003b8cfa
efinix add SCHMITT_TRIGGER support
2024-08-28 19:59:30 +02:00
4ded509444
Merge pull request #2050 from Dolu1990/efinix_pll_ext_fix
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efinix: Fix PLL with external clock input ifacewriter
2024-08-27 09:50:04 +02:00
f8feb8a192
Merge pull request #2048 from trabucayre/colognechip_improve
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Colognechip improve
2024-08-27 09:49:15 +02:00
6d46a5ba05
efinix: Fix PLL with external clock input ifacewriter
2024-08-27 09:02:58 +02:00
0fcc27f58f
build/colognechip/colognechip.py: simplify constrains file with the new toolchain
2024-08-24 12:20:58 +02:00
07e11858c6
soc/cores/clock/colognechip.py: rework/fix locked signal
2024-08-24 12:19:34 +02:00
ef775e0b8e
Merge pull request #2043 from pepijndevos/moreapicula
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fixes for apicula support
2024-08-24 10:37:17 +02:00
4400fbb966
Apicula: add GWINR-18 aliases
2024-08-22 16:02:41 +02:00
6d0ae25d65
Merge pull request #2046 from enjoy-digital/hyperbus_2x
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HyperRAM: Add 2:1 ratio support in addition of 4:1 ratio.
2024-08-21 19:25:41 +02:00
a88cee70c8
test/test_hyperbus: Update.
2024-08-21 19:22:56 +02:00
37823e34b6
soc/cores/hyperbus: Simplify Clk Generation.
2024-08-21 17:10:36 +02:00
ecd9eee5a4
soc/core/hyperbus: Report Clk Ratio on Status register and use it in software to configure latency.
2024-08-21 15:35:21 +02:00
5587f5954d
test/test_hyperbus: Add 2:1 test.
2024-08-21 15:00:11 +02:00
d22669cf05
soc/cores/hyperbus: Handle 4:1/2:1 specific cases separately, default to 4:1 mode (as before).
2024-08-21 12:07:55 +02:00
f6de6e755e
soc/cores/hyperbus: Add cd_io/sync_io.
2024-08-21 11:50:46 +02:00
43879b0f73
soc/cores/hyperbus: Add clk_ratio support to support x1/x2.
2024-08-21 11:41:13 +02:00
22afa34a64
soc/cores/hyperbus: WiP to make increase similarities between x1/x2 versions.
2024-08-21 11:17:55 +02:00
50f0a1057c
soc/cores/hyperbus: Do some tests with sys_2x, seems working.
2024-08-21 10:57:36 +02:00
0b028d3956
soc/cores/hyperbus: Add comment to allow switching to SDRTristate.
2024-08-20 22:05:38 +02:00
60f83b71fa
soc/cores/hyperbus: Avoid dq_oe condition to generate dq_o (was only useful for sim but now avoided).
2024-08-20 21:54:15 +02:00
298a004f08
Merge pull request #2045 from enjoy-digital/hyperbus_io_regs
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Improve HyperRAM core to allow IO Reg inference.
2024-08-20 19:47:01 +02:00
3a37d3ba98
software/libbase/hyperram: Add missing #ifdef.
2024-08-20 17:11:02 +02:00
eb29b40e07
soc/cores/hyperbus: Simplify CS and make it synchronous to allow IO Reg.
2024-08-20 16:19:15 +02:00
1998c74549
soc/cores/hyperbus: Make DQ/RWDS input sync explicit to allow IO Reg.
2024-08-20 15:44:53 +02:00
8b86b16077
soc/cores/hyperbus: Make Rst synchronous to allow IO Reg (even if low speed).
2024-08-20 15:26:26 +02:00
76cf004913
test/test_hyperbus: Update.
2024-08-20 15:17:36 +02:00
b0026937c1
soc/software/libbase: Move HyperRAM init code to libbase/hyperram.c.
2024-08-20 14:58:51 +02:00
a30651e44e
soc/cores/hyperbus: Avoid waiting for clk_phase in IDLE state to reduce latency.
2024-08-20 14:44:33 +02:00
b7605bc633
Merge pull request #2044 from VOGL-electronic/json2dts_zephyr_omit_disabled_handler
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json2dts_zephyr: omit disable handler
2024-08-20 14:29:35 +02:00
bfe000150c
soc/cores/hyperbus: Rework Clk generation to allow having using an IO Reg.
2024-08-20 14:25:23 +02:00
7b413352c2
soc/cores/hyperbus: Directly specify default sys_clk_freq in __init__.
2024-08-20 12:04:23 +02:00
8f5c2dfbca
soc/cores/hyperbus: Fix build with SDRTristate (to prepare tests with it).
2024-08-20 12:03:40 +02:00
3a53a92bb2
soc/cores/hyperbus: Simplify/Rework Data Shift-Out Register.
2024-08-20 11:38:33 +02:00
9c1958d692
soc/cores/hyperbus: Simplify/Rework Data Shift-In Register.
2024-08-20 11:26:58 +02:00
c1403db407
json2dts_zephyr: omit disable handler
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omit disable handler for the sdcard peripherals,
as they still don't have a driver in zephyr and are not in the board dts.
This way the build in zephyr will not fail.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-08-20 11:23:21 +02:00
db86ec08b8
soc/cores/hyperbus: Better split parameters/signals and use intermediate dq_o/oe/i and rwds_o/oe/i signals.
2024-08-20 11:12:17 +02:00
1f71f3d68b
soc/cores/hyperbus: Cleanup CSn/Clk generation and add comments.
2024-08-20 10:40:24 +02:00
a960dc33bc
soc/cores/hyperbus: Minor cleanup changes.
2024-08-20 10:26:34 +02:00
enjoy-digital
Gwenhael Goavec-Merou
Dolu1990
Gwenhael Goavec-Merou
Pepijn de Vos
Fin Maaß