8c5c32751e
add input pipe stage option
2014-10-28 20:53:26 +01:00
bf95ea6c1c
mila: simplify usage
2014-10-10 16:17:12 +02:00
d0c9838dca
uart2wishbone: share UARTRX and UARTTX with MiSoC
2014-10-10 15:15:58 +02:00
ba30a01830
mila: fixes when used without RLE
2014-10-06 12:30:06 +02:00
f72f11f7b4
mila: add clk_domain support
...
an AsyncFIFO is inserted when clk_domain is not "sys" to enable capture from another clock domain.
sys_clk frequency need to be greater than clk_domain clock.
future possible improvement: automatic insertion of a converter when clk_domain frequency is
greater than sys_clk.
2014-10-06 12:07:20 +02:00
7043e6a5f3
mila: simplify export
2014-10-01 10:06:59 +02:00
111f527647
do some clean up
2014-09-24 22:26:33 +02:00
452a4a76f3
use verilog namespace to export mila configuration
2014-08-03 17:09:01 +02:00
f4e6cebab2
clean up
2014-08-03 11:44:27 +02:00
b94cba2d4b
mila: add input pipe to ease timing
2014-05-24 09:23:16 +02:00
1a07116ab1
change export format and simplify usage
2014-05-20 13:16:24 +02:00
ba0382ad92
move some functions in drivers and export layout in csv
2014-05-20 11:36:10 +02:00
2312127c1f
simplify and clean up
2014-05-20 09:56:35 +02:00
7a489b3135
refactor code
2014-04-20 23:53:33 +02:00
69009c8405
mila: test rle
2013-09-22 21:23:51 +02:00
a880862628
mila: symplify usage
2013-09-22 13:28:12 +02:00
27f26dac03
use custom Records instead of Sink/Source (semms easier, but will be reverted if not)
2013-09-22 13:14:11 +02:00
ce9bff21e9
refactoring
2013-09-22 02:49:59 +02:00
5c298f406c
simplify signals connexion
2013-06-02 15:15:47 +02:00
4281a18deb
add stb signal
2013-04-02 21:13:21 +02:00
5e48f9c005
update driver api
2013-03-22 12:35:12 +01:00
b1cbfe2326
clean up/fixes
2013-03-22 11:31:21 +01:00
58edd7632c
compiles but untested
2013-02-28 00:32:42 +01:00
e95e8b03b7
- reworking WIP
2013-02-22 16:40:49 +01:00
Florent Kermarrec