Florent Kermarrec
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002aad7a43
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soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls.
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2023-10-27 10:55:13 +02:00 |
Rafal Kolucki
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8c1bc139ab
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soc/interconnect/wishbone: Cleanup in burst cycles support logic
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2022-04-12 15:32:29 +02:00 |
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Rafal Kolucki
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ad46a57403
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test/test_wishbone: Add test for Wishbone SRAM constant address burst cycle
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2022-04-12 14:06:22 +02:00 |
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Rafal Kolucki
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cdd216f692
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test/test_wishbone: Add basic test for SRAM with burst cycles support
Tests incrementing address burst cycle with linear and wrapped increments.
Only 4-beat wrap burst is tested in `test_sram_burst_wrap` test.
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2022-04-12 14:06:22 +02:00 |
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Florent Kermarrec
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77ae243310
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test: add SPDX License identifier to header and specify file is part of LiteX.
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2020-08-23 15:40:21 +02:00 |
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Florent Kermarrec
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47ce15b431
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interconnect/wishbone: add minimal UpConverter.
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2020-07-21 19:35:14 +02:00 |