Gwenhael Goavec-Merou
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84e376efcb
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build/openocd: jtagstream_rxtx reduce tx to 16 and rx to 128
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2023-12-13 15:08:18 +01:00 |
enjoy-digital
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cdd80a5f4f
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Merge pull request #1433 from tpwrules/faster-jtaguart
Increase JTAG UART upload speed
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2023-12-13 15:05:37 +01:00 |
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enjoy-digital
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5dac2fc16f
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Merge pull request #1852 from trabucayre/increase_cmd_timeout_delay
soc/software/bios/boot: serialboot: increase CMD_TIMEOUT_DELAY
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2023-12-13 14:39:17 +01:00 |
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Gwenhael Goavec-Merou
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00b94a5512
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soc/software/bios/boot: serialboot: increase CMD_TIMEOUT_DELAY
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2023-12-13 14:29:54 +01:00 |
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Florent Kermarrec
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faae1ea95a
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integration/soc/jtag: Switch JTAGPHY to sys_clk/simplify.
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2023-12-13 09:24:23 +01:00 |
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Florent Kermarrec
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4e57cca85f
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cpu/vexriscv: Cleanup reset.
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2023-12-13 09:17:15 +01:00 |
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Florent Kermarrec
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f2c5ff376c
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soc/cores/jtag: Switch to stream.ClockDomainCrossing and use common_rst.
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2023-12-13 09:16:55 +01:00 |
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Gwenhael Goavec-Merou
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94eca8628c
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Revert "soc/integration/soc: add_sdram, remove litedram_wb and converter: let LiteDRAMWishbone2Native dealing with addr/data width"
This reverts commit 6d34b8ed87.
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2023-12-12 15:19:16 +01:00 |
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Gwenhael Goavec-Merou
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6d34b8ed87
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soc/integration/soc: add_sdram, remove litedram_wb and converter: let LiteDRAMWishbone2Native dealing with addr/data width
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2023-12-12 12:05:47 +01:00 |
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Gwenhael Goavec-Merou
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08ff003178
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tools/litex_server.py: jtag/udp mode: add missing addr_width parameter
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2023-12-09 06:08:53 +01:00 |
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Gwenhael Goavec-Merou
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c1871eaf42
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soc/integration/soc: add_jtagbone: pass address_width to UARTBone constructor
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2023-12-09 06:07:58 +01:00 |
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Florent Kermarrec
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acd66f1346
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soc/bus_addressing_convert: Fix s2m adaptation case, the 2 adaptation cases were swapped.
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2023-12-08 15:25:30 +01:00 |
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Florent Kermarrec
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8d6120c476
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CHANGES: Update.
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2023-12-08 12:11:37 +01:00 |
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enjoy-digital
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1e5df2dedf
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Merge pull request #1851 from trabucayre/add_64_bus_support_v2
Add AXI/AXILite 64 bus support
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2023-12-08 12:08:09 +01:00 |
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Gwenhael Goavec-Merou
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2134c0d0b0
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soc/integration/soc: when adding a CSR Bridge bus_bridge must keep bus.address_width instead of the default value
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2023-12-08 12:02:45 +01:00 |
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Gwenhael Goavec-Merou
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1a8fd2e808
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soc/interconnect/axi/axi_full: AXIInterconnectShared, AXICrossbar: propagate master bus address width to Interface
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2023-12-08 12:00:50 +01:00 |
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Gwenhael Goavec-Merou
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13987659a9
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soc/interconnect/axi/axi_lite: AXILiteInterconnectShared, AXILiteCrossbar: propagate master bus address width to Interface
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2023-12-08 11:59:33 +01:00 |
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Gwenhael Goavec-Merou
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01ce8ab0d1
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soc/interconnect/axi/axi_lite:axi_lite_to_simple: avoid multiple read access
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2023-12-08 11:57:35 +01:00 |
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Florent Kermarrec
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afaeca98ce
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CHANGES.md: Update.
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2023-12-07 16:33:32 +01:00 |
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enjoy-digital
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1512080527
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Merge pull request #1850 from trabucayre/efinix_serdes
Efinix PLL calc when feedback != INTERNAL
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2023-12-07 15:05:57 +01:00 |
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Gwenhael Goavec-Merou
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491a207a37
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soc/cores/clock/efinix: calc PLL parameters for Trion when feedback != INTERNAL
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2023-12-07 12:08:28 +01:00 |
Gwenhael Goavec-Merou
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08a62d4b5f
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build/efinix/ifacewriter: PLL feedback for Trion
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2023-12-06 16:58:50 +01:00 |
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Gwenhael Goavec-Merou
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a4ead5cab9
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litex/soc/integration/soc: SoCBusHandler 64bits address width support
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2023-11-30 17:47:32 +01:00 |
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Gwenhael Goavec-Merou
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fba581f77e
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build/efinix/ifacewriter: LVDS_RX/Trion: enable static rx delay when delay > 0
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2023-11-30 17:46:55 +01:00 |
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Florent Kermarrec
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cba58a0e36
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tools/litex_client: Fix csr_data_width/csr_bus_address_width is None cases.
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2023-11-23 16:30:29 +01:00 |
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Florent Kermarrec
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022776801a
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build/efinix/ifacewriter: Ident set_property in generate functions to make it more understandable (for the ones who like black magic... :)
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2023-11-17 12:06:24 +01:00 |
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enjoy-digital
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16bbb8cdd2
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Merge pull request #1843 from trabucayre/efinix_serdes
Efinix Trion serdes
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2023-11-17 11:56:18 +01:00 |
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Gwenhael Goavec-Merou
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fecc0cb227
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build/efinix/ifacewriter: PLL/LVDS serdes: Trion support
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2023-11-17 11:50:58 +01:00 |
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Gwenhael Goavec-Merou
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cbba5b46e9
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build/efinix/efinity: fix 90 phase shift float -> int (yes: WHY?)
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2023-11-17 11:41:00 +01:00 |
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Gwenhael Goavec-Merou
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c8a9f205e0
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soc/cores/clock/efinix: allowing to specify LVDS input refclk name (Trion)
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2023-11-17 11:40:41 +01:00 |
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Florent Kermarrec
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4353135f02
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CHANGES: Update.
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2023-11-16 13:47:17 +01:00 |
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Florent Kermarrec
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aa8e9dc32f
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integration/builder: Add bios_format/--bios-format support to allow selecting printf format and pass it to picolibc.
Useful to printf of float/double is required.
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2023-11-16 12:38:59 +01:00 |
Dolu1990
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6d9cacd465
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core/NaxRiscv update (timing improvements)
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2023-11-14 13:45:01 +01:00 |
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Gwenhael Goavec-Merou
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f41ae88d1c
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soc/cores/clock/efinix: create_clkin: adding lvds_input optional parameter (required when used with LVDS serdes)
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2023-11-14 11:34:13 +01:00 |
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Gwenhael Goavec-Merou
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7cee8e10fd
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build/efinix/ifacewriter: allowing PLL to have LVDS_RX as input type
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2023-11-14 11:24:17 +01:00 |
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Gwenhael Goavec-Merou
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232941be24
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build/efinix/ifacewriter: generate_lvds: adding missing migen import (required by generate_lvds)
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2023-11-14 11:14:57 +01:00 |
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Gwenhael Goavec-Merou
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bf337559fe
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build/efinix/ifacewriter: generate_lvds: adding LVDS serdes support (Titanium only)
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2023-11-14 10:45:16 +01:00 |
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Florent Kermarrec
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edc6871ace
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soc/software: Rename NR_IRQ to CONFIG_CPU_INTERRUPTS.
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2023-11-13 09:14:57 +01:00 |
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Florent Kermarrec
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d7253ffd0e
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integration/soc/add_etherbone: Rename ethernet parameter to with_ethmac and minor cosmetic cleanups.
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2023-11-13 08:57:22 +01:00 |
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enjoy-digital
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2d9a268ff3
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Merge pull request #1838 from motec-research/etherbone
Hybrid Etherbone simplification
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2023-11-13 08:48:29 +01:00 |
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Gwenhael Goavec-Merou
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a18537bf50
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build/gowin/common: disable Tristate (uncorrect code with tangNano9k hypperram #1833)
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2023-11-13 06:34:59 +01:00 |
AndrewD
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968bd28d8b
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Merge pull request #1815 from motec-research/irq_attach
soc/software: add irq_attach() / irq_detach()
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2023-11-13 14:30:48 +11:00 |
Andrew Dennison
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737ced8fa6
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soc/software: add irq_attach() / irq_detach()
cleaner mechanism for other software to use interrupts
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2023-11-13 12:07:35 +11:00 |
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Andrew Dennison
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885d5b9cb1
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tools/litex_sim: update hybrid etherbone integration
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2023-11-13 11:13:19 +11:00 |
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Andrew Dennison
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fb5512f6d5
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soc/integration/soc: simplify hybrid etherbone
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2023-11-13 11:13:10 +11:00 |
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Florent Kermarrec
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77ca872b3b
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tools/litex_sim: Update Etherbone/Ethernet hybrid mode integration.
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2023-11-10 19:13:35 +01:00 |
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Florent Kermarrec
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57782309a2
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integration/soc/add_etherbone: Exclude MAC from CSRs when in hybrid board since added externally.
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2023-11-10 18:59:28 +01:00 |
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Florent Kermarrec
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9f88137ab6
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remote/etherbone: Set default addr_size of 32 (To avoid breaking old code).
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2023-11-10 16:13:43 +01:00 |
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Florent Kermarrec
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52adf240f9
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remote/etherbone/EtherbonePacket: Set default addr_width of 32 (To avoid breaking old code using EtherbonePacket()).
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2023-11-10 13:17:21 +01:00 |
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Florent Kermarrec
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5672a9dd2a
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CONTRIBUTORS: Update.
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2023-11-10 10:35:49 +01:00 |