15 commits

Author	SHA1	Message	Date
Florent Kermarrec	879478a6e4	clocking: clean up and add comments	2014-09-27 13:33:43 +02:00
Florent Kermarrec	387cf90cf8	host and device communicate with OOB, now need to fix ctrl	2014-09-26 23:30:30 +02:00
Florent Kermarrec	01da43ecb2	reset and lock of PLL OK. We see OOB signals on the link but they are not decoded by the device.	2014-09-26 22:31:32 +02:00
Florent Kermarrec	dfbec91a62	add modelsim simulation and start fixing init	2014-09-26 17:05:05 +02:00
Florent Kermarrec	7e14c4fc51	move some logic outside of GTX	2014-09-25 15:23:56 +02:00
Florent Kermarrec	c008dfdd98	clean up (thanks to Sebastien)	2014-09-25 14:17:25 +02:00
Florent Kermarrec	435bc22fa0	integrate phy in test design and start fix syntax errors	2014-09-24 16:07:34 +02:00
Florent Kermarrec	18009303ae	instanciate device or host controller	2014-09-24 14:00:00 +02:00
Florent Kermarrec	60324295fa	manage clock domain crossing and data width conversion in gtx	2014-09-24 13:56:12 +02:00
Florent Kermarrec	f436069a04	create sata clock (sata_tx/2 for a 32 bits data path)	2014-09-24 13:55:06 +02:00
Florent Kermarrec	7790105913	realign rxdata / rxcharisk directly in gtx	2014-09-24 12:13:43 +02:00
Florent Kermarrec	f74471d027	add device ctrl skeleton (we will use it for simulation with the host)	2014-09-24 11:37:28 +02:00
Florent Kermarrec	d78cae1b57	more ctrl skeleton	2014-09-24 11:07:36 +02:00
Florent Kermarrec	71bfd036d0	add ctrl skeleton	2014-09-24 00:01:01 +02:00
Florent Kermarrec	fa509b3365	rearrange code and remove datapath for now	2014-09-23 23:03:32 +02:00