Before this patch, the loop would finish with lowest_div either set to the first failing value
or 0 even if it succeeded with 0. Fix it so that if all tests pass, it’ll end up being -1 before
the incrementation.
This patch also skips retesting the original value. If the retest failed, lowest_div would be incremented past the original value and could potentially wrap around.
* resolve issue #862 add description to soc.svd
The issue is that with no description provided it simply would
not put out a description tag, which breaks compatibility with
other programs.
Insert a somewhat useful default description including a timestamp
and the words "LiteX SoC".
* I2S fix: sample SYNC on the correct edge
The original Tx path implementation samples SYNC on the falling
edge, out of convenience with the fact that teh data must also
change on the falling edge.
This works OK, until you have a CODEC which has a ~40ns max
delay spec on the SYNC, and also has a slightly asymmetric
SYNC edge (the SYNC signal is also the WCLK or LRCLK depending on
which docs you read). The SYNC by spec is supposed to change
on the falling edge, and this extra delay is enough to cause
the SYNC to introduce occassional bit or frame shifts into
the audio.
This fix samples the SYNC on the rising edge, but still
changes the data on the falling edge, thus allowing for
implementations where SYNC has quite loose timings relative
to everything else (as is the case on the TLV320AIC3200)
I am working on testing out the patches from:
https://github.com/litex-hub/linux/pull/8
These linux patches take advantage of the sdcard interrupt to track when
transfers finish. However, it seems the interrupt is not being
connected to the CPU.
This patch does that by allowing us to directly register and
EventManager module with the irq handler.
With recent BIOS changes the default rom size on the mor1kx built just
passes over the 64k boundary and the build fails. Since the 128K
default is a soft limit and the ROM gets resized to the actual ROM
requirements this should be relatively safe.
Note, that if a RW rom is configured the full 128kb will be allocated.
Fixes: #893
When passed as str, the timing dict will be extracted from litex.soc.cores.video.video_timings.
When passed as tuple, custom dict will be directly passed to VTG.
The linker does not actually recognise -nodefaultlibs, that is a compiler
option.
Prior to binutils 2.36, ld treated -nodefaultlibs as a string of short
options and ignored them as unrecognised. Starting from binutils 2.36, it
reports an error instead:
riscv64-unknown-elf-ld: Error: unable to disambiguate: -nodefaultlibs (did you mean --nodefaultlibs ?)
See also: https://sourceware.org/bugzilla/show_bug.cgi?id=27050Fixes#825.
Adding wraps around capability will have to be discussed, if implemented this has to
be done very carefully since there are no relation between the total delay that can
be compensated through the I/O-DELAYs and the SDRAM clock period.
As implemented, it also produced confusing values in the logs:
m0:0 m1:0
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000011111111111111100000| delays: 19+-07
m0, b2: |00000000000000000000000000001111| delays: 14+-17
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |00000000000000000000000000000000| delays: -
m0, b5: |00000000000000000000000000000000| delays: -
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b01 delays: 19+-07
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000011111111111111000000| delays: 19+-07
m1, b2: |00000000000000000000000000001111| delays: 15+-17
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |00000000000000000000000000000000| delays: -
m1, b5: |00000000000000000000000000000000| delays: -
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b01 delays: 19+-07
Switching SDRAM to hardware control.
--> 14+-17 and 15+-17 are confusing.
