Sebastien Bourdeauducq
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76db20cd9f
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fhdl: encapsulate replicated constants
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2011-12-23 00:35:13 +01:00 |
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Sebastien Bourdeauducq
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7456195775
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Consistent names
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2011-12-21 22:57:07 +01:00 |
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Sebastien Bourdeauducq
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4f4d809a4e
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fhdl: better matching of assignment
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2011-12-18 21:49:48 +01:00 |
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Sebastien Bourdeauducq
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dd42b2daff
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fhdl: also take into account object attributes in _make_signal_name. Get rid of declare_signal
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2011-12-18 21:47:29 +01:00 |
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Sebastien Bourdeauducq
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41e2430e2b
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fhdl: automatic signal name from assignment
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2011-12-18 21:26:51 +01:00 |
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Sebastien Bourdeauducq
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d21e095397
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fhdl: fix series of if/elif/else
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2011-12-17 20:31:42 +01:00 |
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Sebastien Bourdeauducq
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c7b9dfc203
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fhdl: simpler syntax
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2011-12-16 21:30:14 +01:00 |
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Sebastien Bourdeauducq
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39b7190334
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Pay a bit more attention to PEP8
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2011-12-16 16:02:55 +01:00 |
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Sebastien Bourdeauducq
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dafef5d744
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fhdl: fix list references (thanks Lars)
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2011-12-11 20:17:29 +01:00 |
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Sebastien Bourdeauducq
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019ef16db4
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fhdl: remove broken fragment iadd
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2011-12-11 01:10:59 +01:00 |
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Sebastien Bourdeauducq
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4b15a84505
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fhdl: fix += for empty fragment
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2011-12-10 20:47:06 +01:00 |
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Sebastien Bourdeauducq
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a49ecc4331
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fhdl: pad support in fragments
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2011-12-10 20:25:24 +01:00 |
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Sebastien Bourdeauducq
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fa63cc1ec8
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fhdl: replication support
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2011-12-09 13:11:34 +01:00 |
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Sebastien Bourdeauducq
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512655c108
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fhdl: improve automatic signal naming
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2011-12-08 21:28:20 +01:00 |
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Sebastien Bourdeauducq
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84eb964adc
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fhdl: support negation operator
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2011-12-08 21:15:44 +01:00 |
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Sebastien Bourdeauducq
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ed05ec5f6a
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instances: signal override
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2011-12-08 18:56:14 +01:00 |
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Sebastien Bourdeauducq
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a6b86168ce
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Simple bus base class
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2011-12-08 18:47:32 +01:00 |
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Sebastien Bourdeauducq
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1b637cea61
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Instance support
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2011-12-08 16:35:32 +01:00 |
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Sebastien Bourdeauducq
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fab02f84cb
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fhdl: fix implicit slice index
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2011-12-07 22:21:30 +01:00 |
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Sebastien Bourdeauducq
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82f77180d5
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fhdl: cleanup value bv
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2011-12-07 22:21:10 +01:00 |
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Sebastien Bourdeauducq
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4340680704
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Cleanup
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2011-12-05 19:25:32 +01:00 |
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Sebastien Bourdeauducq
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ec51f09c98
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Case support + register bank generator
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2011-12-05 17:43:56 +01:00 |
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Sebastien Bourdeauducq
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cd8544c758
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Verilog generator
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2011-12-04 22:26:32 +01:00 |
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Sebastien Bourdeauducq
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499b95a519
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Initial import, FHDL basic structure, divider example
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2011-12-04 16:44:38 +01:00 |