Sebastien Bourdeauducq
dd0f3311cd
structure: remove Fragment.call_sim
2013-03-15 19:15:48 +01:00
Sebastien Bourdeauducq
9b9bd77d00
sim: compatibility with new ClockDomain API
2013-03-15 19:15:28 +01:00
Sebastien Bourdeauducq
6feb6e60b0
New clock_domain API
2013-03-15 18:46:11 +01:00
Sebastien Bourdeauducq
208e039bbb
Local clock domain example
2013-03-15 18:18:32 +01:00
Sebastien Bourdeauducq
bd8bbd9305
Make ClockDomains part of fragments
2013-03-15 18:17:33 +01:00
Sebastien Bourdeauducq
001beadb97
altera_quartus, de0nano: add copyright notices
2013-03-15 12:37:25 +01:00
Sebastien Bourdeauducq
f9e07b92a4
Added platform file for DE0 Nano (by Florent Kermarrec)
2013-03-15 11:41:38 +01:00
Sebastien Bourdeauducq
86d6f1d011
Added support for Altera Quartus (by Florent Kermarrec)
2013-03-15 11:32:12 +01:00
Sebastien Bourdeauducq
71c8172836
xilinx_ise/CRG_SE: reset inversion support
2013-03-15 11:31:36 +01:00
Sebastien Bourdeauducq
37d8029848
CRG: support reset inversion
2013-03-15 10:49:18 +01:00
Sebastien Bourdeauducq
24910173b7
CRG: use new Module API
2013-03-15 10:48:43 +01:00
Sebastien Bourdeauducq
5adab17efa
flow/actor/filter_endpoints: deterministic order
2013-03-14 12:20:18 +01:00
Sebastien Bourdeauducq
fc883198ae
bank/csrgen/BankArray: create banks in sorted order
2013-03-13 23:07:44 +01:00
Sebastien Bourdeauducq
2ae504fb9b
software/bios: default length 4 for mr command
2013-03-13 19:59:39 +01:00
Sebastien Bourdeauducq
eaef3464e9
Instantiate DVI sampler core for both ports
2013-03-13 19:56:56 +01:00
Sebastien Bourdeauducq
e99bafe52b
dvisampler: add core, EDID support
2013-03-13 19:56:26 +01:00
Sebastien Bourdeauducq
52d13959f2
bank/description: modify reg/mem in-place
2013-03-13 19:46:34 +01:00
Lars-Peter Clausen
dea4674922
Allow SimActors to produce/consume a constant stream of tokens
...
Currently a SimActor requires one clock period to recover from consuming or
producing a token. ack/stb are deasserted in the cycle where the token is
consumed/produced and only re-asserted in the next cycle. This patch updates the
code to keep the control signals asserted if the actor is able to produce or
consume a token in the next cycle.
The patch also sets 'initialize' attribute on the simulation method, this will
make sure that the control and data signals will be ready right on the first
clock cycle.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 23:10:51 +01:00
Lars-Peter Clausen
72579a6129
Add support for negative slice indices
...
In python a negative indices usually mean start counting from the right side.
I.e. if the index is negative is acutal index used is len(l) + i. E.g. l[-2]
equals l[len(l)-2].
Being able to specify an index this way also comes in handy for migen slices in
some cases. E.g. the following snippet can be implement to shift an abitrary
length register n bits to the right:
reg.eq(Cat(Replicate(0, n), reg[-n:])
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 21:56:01 +01:00
Sebastien Bourdeauducq
c99cc9343f
examples/pytholite: use new APIs
2013-03-12 16:59:24 +01:00
Sebastien Bourdeauducq
69dbf84e54
sim/generic: support implicit get_fragment
2013-03-12 16:54:01 +01:00
Sebastien Bourdeauducq
d92ca43cd0
vpi: make it work by default on Arch
2013-03-12 16:51:58 +01:00
Sebastien Bourdeauducq
907bfa87f4
examples/basic: use new APIs
2013-03-12 16:45:28 +01:00
Sebastien Bourdeauducq
ecfe1646ec
fhdl/verilog: implicit get_fragment
2013-03-12 16:16:06 +01:00
Sebastien Bourdeauducq
c06a821452
generic_platform: implicit get_fragment
2013-03-12 16:14:13 +01:00
Sebastien Bourdeauducq
1e7783a41e
build.py: use implicit get_fragment
2013-03-12 16:13:20 +01:00
Sebastien Bourdeauducq
4ada2ead05
fhdl/specials/Memory: automatic name#
2013-03-12 15:58:39 +01:00
Sebastien Bourdeauducq
a23df42a7a
Use automatic register naming
2013-03-12 15:47:54 +01:00
Sebastien Bourdeauducq
04df076fba
bank: automatic register naming
2013-03-12 15:45:24 +01:00
Sebastien Bourdeauducq
7e2581bf17
fhdl/tracer: recognize CALL_FUNCTION_VAR opcode
2013-03-12 13:48:09 +01:00
Sebastien Bourdeauducq
12158ceadf
fhdl/tracer: recognize LOAD_DEREF opcode
2013-03-12 10:31:56 +01:00
Sebastien Bourdeauducq
3c75121783
fhdl/tracer: remove leading underscores from names
2013-03-11 22:21:58 +01:00
Sebastien Bourdeauducq
c4d9734e53
README: update
2013-03-11 20:29:47 +01:00
Florent Kermarrec
60e2cdfe79
get_registers --> get_registers_glue since it's conflicting with new Migen register automatic detection
2013-03-11 20:05:30 +01:00
Sebastien Bourdeauducq
80970b203c
bus/asmibus: use implicit finalization
2013-03-11 17:11:59 +01:00
Sebastien Bourdeauducq
b042757187
Fix Register name conflict between Pytholite and Bank
2013-03-10 19:47:21 +01:00
Sebastien Bourdeauducq
a9b723568a
Use new module, autoreg and eventmanager Migen APIs
2013-03-10 19:32:38 +01:00
Sebastien Bourdeauducq
f93695f60e
bank/eventmanager: use module and autoreg
2013-03-10 19:29:05 +01:00
Sebastien Bourdeauducq
174e8cb8d6
bus/asmibus: use fhdl.module API
2013-03-10 19:28:22 +01:00
Sebastien Bourdeauducq
17e0dfe120
fhdl/module: replace autofragment
2013-03-10 19:27:55 +01:00
Sebastien Bourdeauducq
cddbc1157d
bank/description/AutoReg: check that get_memories and get_registers are callable
2013-03-10 18:11:29 +01:00
Sebastien Bourdeauducq
68fe4c269c
bank/csrgen: BankArray
2013-03-10 00:45:16 +01:00
Sebastien Bourdeauducq
f1474420df
bank/description: AutoReg
2013-03-10 00:43:16 +01:00
Sebastien Bourdeauducq
d0676e2dd1
migen/fhdl/autofragment: factorize
2013-03-09 23:23:24 +01:00
Sebastien Bourdeauducq
d0d2df3c4b
fhdl/autofragment: remove legacy functions
2013-03-09 23:05:45 +01:00
Sebastien Bourdeauducq
72fb6fd6bd
fhdl/tools/flat_iteration: generalize
2013-03-09 23:03:15 +01:00
Sebastien Bourdeauducq
f53acb92e7
fhdl/autofragment: fix submodules
2013-03-09 21:15:38 +01:00
Sebastien Bourdeauducq
6da8eb906f
fhdl/autofragment: empty build_fragment by default
2013-03-09 19:10:47 +01:00
Sebastien Bourdeauducq
2b8dc52c13
Use common definition for FinalizeError
2013-03-09 19:03:13 +01:00
Sebastien Bourdeauducq
b75fb7f97c
csr/SRAM: support for writes with memory widths larger than bus words
2013-03-09 00:50:57 +01:00
