Commit Graph

8668 Commits

Author SHA1 Message Date
Florent Kermarrec 7a0056ebf6 cores/ecc: Add initial doc with the help of our new assistant and to test its capabilities :) 2022-12-01 10:27:05 +01:00
Florent Kermarrec c0f31dc843 integration/soc_core: Add default value to soc_core_argdict/ident_version. 2022-11-30 08:46:42 +01:00
Dolu1990 d32149d1a6 Merge branch 'master' into naxriscv-merge 2022-11-25 18:27:12 +01:00
Dolu1990 bf279c0092 cpu/NaxRiscv fix LSU sqcheck 2022-11-25 18:06:13 +01:00
Dolu1990 d5b500762b cpu/NaxRiscv : Update with a smaller LSU, lower latency FPU, self-healing RAS 2022-11-25 16:30:53 +01:00
Gwenhael Goavec-Merou 310bc777b4
Merge pull request #1520 from mkuhn99/master
Zynq7000: Implement function to add axi gp slave
2022-11-23 19:30:38 +01:00
mkuhn99 2630ccbc43 impemented add_axi_gp_slave function for zynq7000 core 2022-11-23 17:02:42 +01:00
Florent Kermarrec 143e08575c build/xilinx/vivado: Cleanup location of bistream/additional commands. 2022-11-23 11:17:00 +01:00
Florent Kermarrec f9d2eec06f integration/export: Directly generate extract/replace mask in Python (Fix compilation warning with size=32). 2022-11-22 10:13:22 +01:00
Florent Kermarrec c8197b1842 integration/export: Fix CSR base address definition when with_csr_base_define=False.
We don't want base address to be function express with CSR_BASE but still want base address to be defined.
2022-11-21 17:57:48 +01:00
Florent Kermarrec 4b22a7b109 build/osfpga: Add fake OSFPGAAsyncResetSynchronizer and false_path_constraint to be able to generate more cores.
Code will be replaced when information will be available.
2022-11-21 12:31:06 +01:00
Florent Kermarrec 9a8c19d3b0 build/sim/verilator: Also exclude .init files. 2022-11-21 11:26:21 +01:00
Florent Kermarrec 2c9ddc20be ci: Switch GCC toolchain install to litex_setup.py (to also cover litex_setup.py GCC toolchain install in CI). 2022-11-21 09:20:22 +01:00
Florent Kermarrec dd91c55c36 litex_setup.py: Switch GCC toolchain install to distro install (When available). 2022-11-21 09:17:13 +01:00
enjoy-digital c4cf5d6fcd
Merge pull request #1519 from shenki/use-distro-compilers
github: Use distibution compilers for riscv and or1k
2022-11-21 09:16:02 +01:00
enjoy-digital 3d53f88262
Merge pull request #1518 from shenki/bump-microwatt
litex_setup: Update Microwatt to latest
2022-11-21 08:24:48 +01:00
enjoy-digital 9bb1a261dc
Merge pull request #1517 from shenki/nerov32
test_cpu: Add NeoRV32 to tested CPUs
2022-11-21 08:24:25 +01:00
Joel Stanley b30dd0b5c6 test_cpu: Add NeoRV32 to tested CPUs
With CI supporting GHDL to convert VHDL to Verilog the neorv32
simulation can be tested.

Fixes https://github.com/enjoy-digital/litex/issues/1320

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-21 15:20:49 +10:30
Joel Stanley 76f7cf8b52 github: Use distibution compilers for riscv and or1k
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-21 14:47:53 +10:30
Joel Stanley 8b7c569fac litex_setup: Update Microwatt to latest
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-21 14:41:01 +10:30
Florent Kermarrec 6b4696e3e0 soc/add_spi_flash: Use name as prefix for defined constants.
Allow adding multiple SPIFlash with different names to the SoC. The BIOS will
only use "spiflash" for now but the other SPI Flash core will  be accessible.
2022-11-18 18:31:19 +01:00
Florent Kermarrec c957ed6ed3 README.md: Update Discord invitation link (permanent). 2022-11-18 09:00:05 +01:00
enjoy-digital cc4ae21795
Merge pull request #1515 from shenki/ci-ubuntu-22.04
Update CI to use Ubuntu 22.04
2022-11-18 08:57:44 +01:00
Florent Kermarrec db87fa1a7f LICENSE: Move moral precisions to README.md to be OSI compliant and rephrase to avoid any limitation but at least make things clear and written.
Fix #1514.

Precisions made to the LICENSE were not legal modifications to the License, just some moral precisions since things don't seemed clear for everyone.
(Won't elaborate on this, but were some reasons add these precisions).


These precisions are just willing to protect the work of the community/developers and allow the project  to continue being developed with a
BSD 2-Clause License: ie share almost everything that is developed, without even thinking about potential business opportunities.

Since moral aspects seems to be modifying the license, these are just integrated in the README.md and are still a condition to:
- Expect the community to be welcoming.
- Expect free or even paid support (moral/integrity is more important than $$$ for us).
- Expect the contributions to be accepted/integrated.

So if you don't want to respect the moral precisions, up to you to use the project, but please
be coherent with yourself and don't use our time/energy; just improve/implement things by yourself :)
2022-11-18 00:17:11 +01:00
Florent Kermarrec f66852b975 interconnect/wishbone: Revert #1505 for now sine seem to introduce some regressions.
This will need to be understood and covered by simulations.
2022-11-17 12:34:01 +01:00
Joel Stanley 5e43a0a52b github: Update actions
Avoids the warning "Node.js 12 actions are deprecated". No changes in
behaviour are expected.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-17 21:34:08 +10:30
Florent Kermarrec 4b238005f7 README.md: Add LiteX Discord server link. 2022-11-16 09:29:51 +01:00
Joel Stanley 917c839c30 github: Update to Ubuntu 22.04
Move to the latest Ubuntu LTS for updated tooling. This requires us to
drop the zlibc package which no longer exists, and doesn't appear to be
required. Also update to the master branch of the GHDL action as this
contains 22.04 support.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-15 23:08:17 +10:30
Florent Kermarrec a092927139 cores/cpu: Revert custom __init__ (Required by CPUNone designs). 2022-11-15 13:16:50 +01:00
Florent Kermarrec 4baeeed946 soc/cores/cpu: Add reset_address_check attribute and enable/disable methods and use it to disable CPU Reset Address check in Soc.
For designs willing to put the reset address of the CPU in a region not directly handled by LiteX,
self.cpu.disable_reset_address_check() can be used in the SoC to disable CPU reset address check.
2022-11-15 12:03:11 +01:00
enjoy-digital 703bd16a96
Merge pull request #1505 from antmicro/fix-wishbone-arbiter
Fix Wishbone arbiter
2022-11-15 10:11:59 +01:00
enjoy-digital 4afee8535b
Merge pull request #1504 from antmicro/msieron/fix-etherbone-timeouts
remote/comm_udp: Fix Etherbone timeout errors
2022-11-15 10:10:08 +01:00
enjoy-digital b90080ab74
Merge pull request #1503 from shenki/microwatt-ci
Add Microwatt CI
2022-11-15 10:06:22 +01:00
Maciej Dudek 07184d37df Fix Wishbone arbiter
Right now, when multiple masters want to access the bus,
access is granted to one of them, and is not revoked until
selected master has finished all of its transactions (cyc goes low).

This state causes master starvation if access is granted to high
bandwidth master, like cpu in busy loop.

This commit makes it so access to bus is revoked when pending transaction
is finished (ack and cyc are high) or when selected master is idle.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2022-11-14 21:31:24 +01:00
Michal Sieron 9ae0da667b remote/comm_udp: Fix Etherbone timeout errors
This commit fixes a bug where, retry after timeout would send another
request, but wouldn't discard a response that arrived after the timeout.

Retries worked, but only for dropped packets. If a response arrived, but
`socker.recvfrom` timed out, response would still be put in receive
queue. Later after sending another request, client would try to read
from the socket and would find a response. But this response would be
for the old request.
This way request/response pairs would get misaligned and stop working
properly.

This commit adds read numbering (writes do not have responses).
Numbering is achieved by utilizing the fact that responses to Etherbone
reads are actually writes to an address specified in a request.
This way, we don't need to extend Etherbone protocol, in fact we use it
as it is intended.

This numbering is then used to discard responses that don't match
current request.

I also cleaned setting of the timeout, as it was being set in multiple
places, sometimes to values so small that retry was bound to happen.

Signed-off-by: Michal Sieron <msieron@antmicro.com>
2022-11-14 21:24:37 +01:00
Joel Stanley b0b57491bb test_cpu: Add Microwatt to tested CPUs
Now that LiteX can convert from VHDL to Verilog using GHDL, and the
required dependencies are installed in the CI environment, start testing
Microwatt.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-14 22:09:47 +10:30
Joel Stanley f89746af9f github: Add ppc64le toolchain
The toolchain is used by microwatt.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-14 22:07:20 +10:30
Joel Stanley 25969237f5 github: Add GHDL to build environment
GHDL provides a github action that adds a nightly build to the CI
environment:

 https://github.com/ghdl/setup-ghdl-ci

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-14 22:07:20 +10:30
Joel Stanley b340b86975 test_cpu: Set number of verilator jobs
By default verilator will be built with -j with no arguments, spawning
many processors. This causes large designs to failure in CI (probably
due to exhausting the memory of the build box):

 Error: Process completed with exit code 143.

Set the number of jobs to the number of CPUs in the system. This allows
designs such as Microwatt to build in CI.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-14 22:05:54 +10:30
Florent Kermarrec 05b0c59607 interconnect: For now remove the address_width checks; more verification will have to be done before enabling it to avoid regressions. 2022-11-14 10:34:48 +01:00
Florent Kermarrec 9115db5023 soc/cores/video/VideoS7GTPHDMIPHY: Fix typo (probably related to some refactoring). 2022-11-14 09:54:55 +01:00
Florent Kermarrec ec126f0e4d test/test_cpu: Move ibex to untested_cpus since seems to be broken since 2022.11.12. 2022-11-14 09:51:37 +01:00
Florent Kermarrec 269525862b interconnect/axi/axi_lite_to_simple: Avoid combinatorial loop on ax.valid/ax.ready. 2022-11-14 09:34:10 +01:00
Florent Kermarrec 82127043c3 interconnect: Add data_width/address_width checks on InterconnectShared/Crossbar and also propagate address_width. 2022-11-14 09:08:28 +01:00
Florent Kermarrec a3cc741d26 interconnect: Ensure data_width is propagated on all InterconnectShared/Crossbar modules. 2022-11-14 08:34:38 +01:00
enjoy-digital 68c34c64b0
Merge pull request #1501 from bunnie/axi-full-xbar-datawidth
AXICrossbar: absorb data width setting when building crossbar
2022-11-14 08:24:23 +01:00
bunnie d741346f63 AXICrossbar: absorb data width setting when building crossbar
This patch allows the AXICrossbar to absorb non-default datawidths
when the crossbar is built.

e.g. in the case of a 64-bit AXICrossbar, without this patch the
crossbar was only connecting the bottom 32 bits.
2022-11-12 18:29:51 +08:00
enjoy-digital a7475d7f96
Merge pull request #1500 from cklarhorst/cd_fix
core/naxriscv: Don't use os.system to execute sbt
2022-11-12 11:00:36 +01:00
Christian Klarhorst c1c4910d67 core/naxriscv: Don't use os.system to execute sbt
The use of os.system together with cd is a problem because it changes the
CWD for the whole python process. This breaks for example --csr-csv.
2022-11-11 14:14:47 +01:00
Florent Kermarrec c1885b333f build/altera/platform: Don't set keep attribute on clk signal when using add_period_constraints.
This was preventing the build with Quartus.
2022-11-11 10:06:20 +01:00