Commit Graph

10 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 50ed73c937 New specification for width and signedness 2012-11-29 21:22:38 +01:00
Sebastien Bourdeauducq 5183774ec8 bus/wishbone2asmi: do not use MemoryPort 2012-11-26 19:14:59 +01:00
Sebastien Bourdeauducq 68cd445662 bus/wishbone2asmi: fix cache tag size 2012-05-15 15:18:03 +02:00
Sebastien Bourdeauducq 0bea1e2589 asmi: dat_wm high to disable data write 2012-05-15 14:41:54 +02:00
Sebastien Bourdeauducq 5c0cc6292c fhdl: export log2_int 2012-03-14 12:19:42 +01:00
Sebastien Bourdeauducq 0493212124 bus: simplify and cleanup
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
2012-02-15 16:30:16 +01:00
Sebastien Bourdeauducq e11d9b9322 bus/wishbone2asmi: cache hits working 2012-02-13 23:11:16 +01:00
Sebastien Bourdeauducq 264be80f2d Fix syntax errors and other stupid problems 2012-02-13 22:28:02 +01:00
Sebastien Bourdeauducq 060426cb59 bus/wishbone2asmi: set WM, and send 0 when inactive 2012-02-13 16:49:43 +01:00
Sebastien Bourdeauducq cad9d3b960 bus: Wishbone to ASMI caching bridge (untested) 2012-02-13 16:29:38 +01:00