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4621 Commits

Author SHA1 Message Date
Jean-François Nguyen 8f377307d8 add Minerva support 2018-09-05 22:33:04 +02:00
Florent Kermarrec 1944289e64 litex_server: update pcie and remove bar_size parameter 2018-09-05 13:01:51 +02:00
Tim Ansell c5a2d6f3ec
Merge pull request #96 from cr1901/tinyfpga_bx 
build/platforms: Add TinyFPGA BX board and programmer.
 2018-09-03 20:49:33 -07:00
William D. Jones 2949262449 build/platforms: Add TinyFPGA BX board and programmer. 2018-09-03 23:39:40 -04:00
Tim Ansell 3cb754da74
Merge pull request #95 from cr1901/lm32-lite 
Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly.
 2018-09-03 20:13:45 -07:00
William D. Jones ed507d618d Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly. 2018-09-03 19:48:19 -04:00
Florent Kermarrec 28cd2da24e README: update 2018-08-31 08:44:22 +02:00
enjoy-digital 05c7b9daf4
Merge pull request #94 from cr1901/nextpnr 
lattice/icestorm: Add nextpnr pnr as alternate pnr tool.
 2018-08-28 11:46:35 +02:00
William D. Jones 7af89efc70 lattice/icestorm: Add nextpnr pnr as alternate pnr tool. 2018-08-28 05:17:32 -04:00
Tim Ansell 7a14b75cd6
Merge pull request #93 from phlipped/master 
Fix URL for liteUSB
 2018-08-24 14:08:28 +10:00
phlipped 8b51c44506
Fix URL for liteUSB 2018-08-24 14:03:16 +10:00
Tim Ansell 0074bb888c
Merge pull request #91 from cr1901/ignore-fix 
.gitignore: litex/build contains valid source, so exclude from .gitig…
 2018-08-23 13:17:40 +10:00
Tim Ansell ff908e404f
Merge pull request #92 from cr1901/l2-gate 
software/bios: Gate flush_l2_cache() if L2 Cache isn't present.
 2018-08-23 13:15:49 +10:00
William D. Jones dd480eb72c .gitignore: litex/build contains valid source, so exclude from .gitignore. 2018-08-22 23:04:20 -04:00
William D. Jones 3146109af3 software/bios: Gate flush_l2_cache() if L2 Cache isn't present. 2018-08-22 23:03:08 -04:00
Florent Kermarrec 759e7d4dc3 bios/sdram: improve/simplify read window selection 
Compute a score for each window and select the best
 2018-08-22 23:15:32 +02:00
Florent Kermarrec 09776b77e6 sim: run as root only when needed (ethernet module present) 2018-08-22 15:20:28 +02:00
Florent Kermarrec 06e835a3f8 builder: change call to get_sdram_phy_c_header and also pass timing_settings 2018-08-22 14:28:37 +02:00
Florent Kermarrec ee26f8c5ae soc_sdram: cosmetic 2018-08-22 13:40:22 +02:00
Florent Kermarrec 2db5424ae6 soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >) 2018-08-22 13:28:23 +02:00
Florent Kermarrec 45e9a42c7e soc_core: add cpu_endianness 2018-08-21 19:10:22 +02:00
Florent Kermarrec 3877d0f111 builder: get_sdram_phy_header renamed to get_sdram_phy_c_header 2018-08-21 18:15:57 +02:00
Florent Kermarrec c64e44ef3f soc_sdram: use new LiteDRAMWishbone2Native and port.data_width 2018-08-21 14:52:28 +02:00
Florent Kermarrec 2eeccc5054 vexriscv: update 2018-08-21 11:04:15 +02:00
Florent Kermarrec eecc6f68ed soc/integration: move sdram_init to litedram 2018-08-20 15:36:51 +02:00
Florent Kermarrec 077f939169 Vexriscv: update csr-defs.h 2018-08-18 14:15:43 +02:00
Florent Kermarrec 4225c3b87c update Vexriscv 2018-08-18 14:14:00 +02:00
Florent Kermarrec 9547938527 bios/sdram: changes to ease manual read window selection 2018-08-18 13:45:22 +02:00
Florent Kermarrec a760322fbd litex_server: allow multiple clients to connect to the same server 2018-08-17 16:09:08 +02:00
Florent Kermarrec 8a69a47e7b cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) 2018-08-17 08:32:32 +02:00
Florent Kermarrec cb5b4ac468 bios/boot: flush all caches before running from ram 2018-08-16 19:47:43 +02:00
Florent Kermarrec 650ac18685 sim/verilator: catch ctrl-c on exit and revert default termios settings 2018-08-16 15:13:27 +02:00
Florent Kermarrec 0831ad5492 cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf 2018-08-16 10:04:09 +02:00
Florent Kermarrec 1610a7f3fb bios/sdram: fix read_level_scan result 2018-08-14 18:33:36 +02:00
enjoy-digital e07ca05749
Merge pull request #86 from pgielda/patch-1 
Fix generating csr.csv file
 2018-08-12 19:34:52 +02:00
Peter Gielda 3c7890cdd4
Fix generating csr.csv file 
Fix generating csr.csv file when no absolute path is given.
 2018-08-12 13:37:39 +02:00
Florent Kermarrec 9fa234da50 soc/intergration/cpu_interface: typo 2018-08-08 08:53:54 +02:00
Florent Kermarrec 22f645adc1 bios/main: use edata instead of erodata 2018-08-07 09:02:09 +02:00
Florent Kermarrec 580efecc8c picorv32: add reset signal 2018-08-07 08:59:34 +02:00
Florent Kermarrec 0429ee9f8f soc/software/bios: add reboot command 2018-08-06 12:23:50 +02:00
Florent Kermarrec da75159814 soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers 2018-08-06 12:23:16 +02:00
Florent Kermarrec 8ba5625227 soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error. 2018-08-06 12:21:18 +02:00
Florent Kermarrec c0989f65dd soc/cores/cpu: add reset signal 2018-08-06 12:19:23 +02:00
enjoy-digital 380f8b96dd
Merge pull request #81 from xobs/vexriscv-to-wishbone 
Push Vexriscv debug directly on the Wishbone bus
 2018-07-27 11:59:28 +02:00
Sean Cross fb145daced tools: remove vexriscv_debug 
This program is no longer needed.

The `openocd_vexriscv` package natively supports `etherbone`, and now
that the vexriscv debug module is available on Wishbone instead of as a
CSR, this module no longer works.

This change simplifies both tooling (because there is one fewer program
to run) and integration (because you don't need to modify your CSRs
anymore, just `register_mem()`.)

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-27 15:25:33 +08:00
Sean Cross f17b8324d4 vexriscv: reset wishbone bus on CPU reset 
If the CPU is resetting during a Wishbone transfer, assert the ERR line.

Because the resetOut line is likely multiple cycles long, this should
give Wishbone enough time to finish its transfer, which will cause d.stb
and i.stb to go to 0, which will return d_err and i_err to 0.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-27 15:24:43 +08:00
Sean Cross c87ca4f1c3 vexriscv: put debug bus directly on wishbone bus 
By placing the VexRiscv debug bus on the Wishbone bus, the Etherbone
core can access 32-bit values directly from the core.  Additionally,
both reading and writing are supported without the need to do a SYNC
register as before.

Additionally, the address of the Wishbone bus won't move around anymore,
as it's fixed when doing `self.register_mem()`.

Signed-off-by: Sean Cross <sean@xobs.io>
 2018-07-27 15:24:43 +08:00
Florent Kermarrec 20d6fcac61 add litex_setup script to clone and install Migen, LiteX and LiteX's cores 2018-07-20 10:11:41 +02:00
Florent Kermarrec 8a311bf4a6 build/generic_platform: use list for sources instead of set 
Ideally, we want to use an ordered set (to be able to keep compilation order), to avoid using an external package, we use a list.
 2018-07-20 10:01:33 +02:00
Florent Kermarrec df7e5dbcf6 bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup 2018-07-19 12:52:00 +02:00