34a9303448
Fix for missing connectors for arty boards
2018-05-24 21:55:52 +03:00
e7d1683e34
litex_term: cleanup getkey and revert default settings on KeyboardInterrupt
2018-05-24 08:10:05 +02:00
06162b61cb
README: add list of supported CPUs/Cores and add link to tutorials
2018-05-09 16:28:28 +02:00
6854c7f5fc
soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/ )
2018-05-09 15:39:25 +02:00
66229c8c05
add VexRiscv support (imported/adapted from misoc)
2018-05-09 15:03:37 +02:00
f60da4a5dc
add VexRiscv submodule
2018-05-09 14:39:31 +02:00
d149f386c9
allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32)
2018-05-09 13:26:55 +02:00
c3652935d9
build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation)
2018-05-01 12:02:54 +02:00
121eaba722
soc/intergration/soc_core: don't delete uart/timer0 interrupts
2018-05-01 00:46:26 +02:00
39ffa532b0
xilinx/programmer: fix programmer
2018-05-01 00:44:13 +02:00
c001b8eaf6
build/xilinx/vivado: add vivado ip support
2018-04-12 17:55:46 +02:00
43f8c230a7
soc_core: uncomment uart interrupt deletion
2018-04-12 17:23:46 +02:00
d7c7474670
gen/sim: fix import to use litex simulator instead of migen simulator
2018-04-04 15:40:53 +02:00
b7f7c8d159
build/xilinx/common/XilinxDDROutputImplS6: DDR_ALIGNMENT="C0" requires SRTYPE to be "ASYNC"
2018-03-12 09:33:05 +01:00
4324c6f666
bios/sdram: update kuddrphy initialization procedure
2018-03-08 13:54:30 +01:00
90dcd45f0b
soc/software/main: go to new line at startup
2018-03-07 21:39:10 +01:00
6706b24167
software/bios/main: add missing space
2018-03-07 15:24:39 +01:00
2a50a8021a
soc/integration/soc_core: improve error message for missing csrs
2018-03-05 09:59:06 +01:00
c02b127ef9
Merge pull request #68 from mithro/improve-csr-missing-error-message
...
Improving error message when csr name is not found.
2018-03-05 08:38:25 +01:00
3e7cc2554b
Merge pull request #69 from mithro/conda-support
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Adding conda environment and simple travis build
2018-03-04 19:50:39 +01:00
3bf5047954
travis: Adding some color.
2018-03-03 18:17:55 -08:00
083c261364
travis: Move the conda install into script so it can be folded.
2018-03-03 17:47:11 -08:00
da3189c8b5
travis: Making the output more readable.
2018-03-03 17:28:42 -08:00
12bb3ebf7c
travis: Build all the SoCs (without gateware).
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- TODO: Build the simulator SoC.
2018-03-03 16:49:49 -08:00
e65c121adf
Adding a travis config which tests the conda environment still works.
2018-03-03 16:42:33 -08:00
795e82858f
Adding conda environment example.
...
This is a very light weight way of doing something similar to the
litex-buildenv.
2018-03-03 16:30:09 -08:00
5ef34500f7
Improving error message when csr name is not found.
...
Before;
```
"/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/integration/soc_core.py",
line 258, in get_csr_dev_address
return self.csr_map[name]
KeyError: 'core'
```
Now;
```
Traceback (most recent call last):
File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 259, in get_csr_dev_address
return self.csr_map[name]
KeyError: 'ddrphy'
The above exception was the direct cause of the following exception:
Traceback (most recent call last):
...
File "XXXX/github/enjoy-digital/litex/litex/soc/interconnect/csr_bus.py", line 199, in scan
mapaddr = self.address_map(name, None)
File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 269, in get_csr_dev_address
) from e
RuntimeError: Unable to find ddrphy in your SoC's csr address map.
Check BaseSoC.csr_map in XXXX/github/enjoy-digital/litex/litex/boards/targets/arty.py
Found l2_cache, timer0, ddrphy2, buttons, sdram, identifier_mem, uart, uart_phy, leds, crg in the csr_map
```
2018-03-03 16:02:44 -08:00
ab2a3277c3
Merge pull request #67 from cr1901/vivado-paths
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xilinx/vivado: Provide a fallback mechanism for using the same root f…
2018-03-03 08:29:18 +01:00
db20df49f4
Merge pull request #65 from cr1901/tinyfpga-serial
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platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it
2018-03-03 08:28:57 +01:00
2b00b7eba4
xilinx/vivado: Provide a fallback mechanism for using the same root for Vivado and ISE toolchains.
2018-03-02 21:48:49 -05:00
fa6b256198
build/xilinx/platform: fix merge
2018-03-03 00:07:50 +01:00
87d4af0bc0
Merge pull request #66 from cr1901/arty_s7
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boards/arty_s7: Fix IOStandard on System Clock.
2018-03-02 12:11:35 -08:00
d40c57739c
boards/arty_s7: Fix IOStandard on System Clock.
2018-03-02 13:35:43 -05:00
7bd718eb55
README: add migen installation to quick start guide
2018-03-01 10:15:43 +01:00
0332f73a7b
build/xilinx/vivado: revert toolchain_path
2018-02-28 23:45:26 +01:00
2ff50a8882
build: fix merge
2018-02-28 23:10:24 +01:00
64e4e1ce84
build: merge with migen.build 27beffe7
2018-02-28 16:49:12 +01:00
0edfd9b901
boards/kcu105: regroup sfp tx and rx
2018-02-28 14:11:58 +01:00
e71593d67e
platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it
...
optional via `add_extension`.
2018-02-27 18:41:35 -05:00
c5be6e26be
README: add section for newcomers
2018-02-23 14:37:10 +01:00
f372e8c880
README: cleanup
2018-02-23 14:15:41 +01:00
fb088b79dd
README: update, migen is no longer forked
2018-02-23 14:08:13 +01:00
1925ba176f
replace litex.gen imports with migen imports
2018-02-23 13:38:19 +01:00
43164b9a2c
remove migen fork from litex
2018-02-23 13:37:26 +01:00
212e1a7076
bump to 0.2.dev
2018-02-23 13:36:32 +01:00
64aa4ae4c0
uniformize with litex cores and make things more clear about what LiteX vs Migen/MiSoC
2018-02-22 11:52:10 +01:00
aaf097056a
Merge pull request #64 from q3k/q3k/axi4lite
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Preliminary AXI4Lite support: CSR bridge
2018-02-21 09:47:29 +01:00
688f26cc32
Change AXI interface and tidy code
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Inspired by parts of https://github.com/peteut/migen-misc/
2018-02-21 00:00:58 +00:00
512ed2b3d6
Preliminary AXI4Lite CSR bridge support
...
This change introduces an AXI4Lite to CSR bridge. Hopefully it will
become extended in the future with full AXI support and more structures
(Wishbone bridge, interconnect, ...). For now this will do.
The bridge has been simulated (and includes an FHDL testbench) and
tested in hardware (on a Zynq 7020).
2018-02-20 21:27:51 +00:00
55fc9d2d6b
Merge pull request #60 from q3k/for-upstream/top-level-module-selection
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Top module selection (for Verilator and Diamond)
2018-02-19 12:27:25 +01:00
Deano Calver
Florent Kermarrec
Dolu1990
Tim 'mithro' Ansell
William D. Jones
Sergiusz Bazanski