Leon Schuermann
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727cc40ab1
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Add missing soc/cores/cpu directories to MANIFEST.in
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2022-08-09 20:30:04 +02:00 |
Florent Kermarrec
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b485829ec4
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MANIFEST.in: update.
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2021-02-08 10:11:10 +01:00 |
Arnaud Durand
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5e049d8966
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Add data dirs to manifest
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2020-05-05 22:15:24 +02:00 |
Tim 'mithro' Ansell
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3aee8a5227
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Remove directories from submodules from MANIFEST.in file.
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2020-04-11 18:37:06 -07:00 |
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Arnaud Durand
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68eeba9181
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Add verilog submodule from CPU cores to manifest
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2019-07-04 00:58:26 +02:00 |
|
Florent Kermarrec
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17f6cb1f17
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initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush)
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2016-04-01 00:09:17 +02:00 |
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Florent Kermarrec
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a775672314
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litex: get verilator simulation working and add sim target as example
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2015-11-07 23:51:37 +01:00 |
|
Florent Kermarrec
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6a0f85dc42
|
litex: reorganize things, first work working version
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2015-11-07 17:48:55 +01:00 |
|
Florent Kermarrec
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b028569784
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import misoc in litex/soc
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2015-11-07 12:19:30 +01:00 |
Sebastien Bourdeauducq
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766b0bee65
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MANIFEST.in: fix lm32 data directory
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2015-10-19 16:30:41 +08:00 |
|
Sebastien Bourdeauducq
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e96eba4493
|
setup: include software and Verilog files
Broken on Python 3.5
error: can't copy 'misoc/software': doesn't exist or not a regular file
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2015-10-05 12:08:02 +08:00 |