Florent Kermarrec
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a5ed42ec68
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soc/interconnect/stream: add Gearbox
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2018-11-17 17:29:45 +01:00 |
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Florent Kermarrec
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11d536dc4d
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test: remove test_bitslip (integrated in migen)
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2018-11-17 17:29:09 +01:00 |
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Florent Kermarrec
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0b0e3ac1dd
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test/test_targets: test simple design with all platforms
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2018-09-24 02:02:14 +02:00 |
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Florent Kermarrec
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e04530e0c4
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test/test_targets: update and reorganize targets
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2018-09-24 01:15:33 +02:00 |
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Florent Kermarrec
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1925ba176f
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replace litex.gen imports with migen imports
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2018-02-23 13:38:19 +01:00 |
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Florent Kermarrec
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e0ce485a17
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test/test_gearbox: continue, but we are hitting a simulator bug (related to clock domains declared in modules)
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2017-04-25 10:57:34 +02:00 |
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Florent Kermarrec
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3ca0cb0cea
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test: add test_gearbox skeleton
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2017-04-24 21:41:46 +02:00 |
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Florent Kermarrec
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b4ebfb4031
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test/test_targets: check top.v generation
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2017-04-24 19:25:58 +02:00 |
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Florent Kermarrec
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35e3d93d9b
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test: add basic test_targets.py
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2017-04-24 19:13:17 +02:00 |
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Florent Kermarrec
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dc66dfcb55
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test: add test_bitslip (initially in litedram)
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2017-04-24 18:50:06 +02:00 |
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Florent Kermarrec
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96898f1b39
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add test directory with test_code_8b10b.py (from misoc)
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2017-04-24 18:46:55 +02:00 |