a7a70fa2f0
tools/litex_json2dts: Fix mmc node
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mmc@f0006800:reg:0: [4026558464, 256, 4026560512, 256, 4026562560, 256, 4026564608, 256] is too long
From schema: dt-schema/dtschema/schemas/simple-bus.yaml
mmc@f0006800:reg:0: [4026558464, 256, 4026560512, 256, 4026562560, 256, 4026564608, 256] is too long
From schema: dt-schema/dtschema/schemas/reg.yaml
Fix this by grouping the tuples in the "reg" property using angle
brackets.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-03-26 17:19:01 +01:00
54d2578f04
tools/litex_json2dts: Fix liteuart node
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serial@f0001000: 'device_type' does not match any of the regexes: 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/serial/litex,liteuart.yaml
Fix this by dropping the offending property.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-03-26 17:19:01 +01:00
bcef9a68ca
tools/litex_json2dts: Fix plic node
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interrupt-controller@f0c00000: compatible:0: 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'canaan,k210-plic']
From schema: Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
interrupt-controller@f0c00000: compatible:1: 'sifive,plic-1.0.0' was expected
From schema: Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
interrupt-controller@f0c00000: '#address-cells' is a required property
From schema: Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
Fix this by correcting the order of the compatible values, and adding
the missing #address-cells property.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-03-26 17:19:01 +01:00
610bfe4d0c
tools/litex_json2dts: Fix DTS indentation
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- Replace bogus TAB by spaces,
- Drop spaces from empty lines.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-03-26 17:19:01 +01:00
6b482bce54
tools/litex_json2dts/framebuffer: Switch to new simplified Video Framebuffer.
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Timings are already pre-initialized, so software will only have to configure/modify
them to change the video resolution.
2021-03-26 16:25:06 +01:00
137274dfe0
integration/soc/add_video_framebuffer: Use mem_map for video base address (or defaults to 0x4800000) and pass constants to software.
2021-03-26 16:23:30 +01:00
ed1d29958a
cores/video/VideoFrameBuffer: Fix colors ordering.
2021-03-26 16:22:12 +01:00
714903e65b
cores/video/VideoTerminal: Write CSI interpreter color to term_mem (\e[92;1m\e[0m decoding working).
2021-03-26 11:15:27 +01:00
18f77ef378
cores/video/VideoTerminal: Also do a CLEAR-X after RST-X (Fix issue with lines displayed with previous contents).
2021-03-26 10:35:02 +01:00
438eec0268
integration/soc/add_sdcard: Re-Remove self.csr.add (was a false alarm, this also works with Linux-on-LiteX-Rocket).
2021-03-26 08:45:32 +01:00
60d518a5d3
Merge pull request #864 from gsomlo/gls-json2dts-eth
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json2dts.py: fix mac0 reg property style for consistency
2021-03-26 08:33:14 +01:00
c859c34844
json2dts.py: fix mac0 reg property style for consistency
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Assuming "#[address|size]-cells = <1>", both of the following are
equivalent:
reg = <start1 size1>, <start2 size2>, ..., <startN sizeN>;
reg = <start1 size1 start2 size2 ... startN sizeN>;
The second form appears more widely used and popular, including in
the output of json2dts.py, with the exception of the mac0 node, which
uses the first form. This patch makes output generated for mac0
consistent with that for other DT nodes.
2021-03-25 15:50:12 -04:00
58701cc48c
tools/litex_client: Use CSR base as base address on PCIe designs.
2021-03-25 18:25:37 +01:00
518aaeaacb
Merge pull request #863 from Dolu1990/master
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cpu/vexriscv_smp add RVC support
2021-03-25 16:26:30 +01:00
4246f77a97
integration/soc/add_scard: Revert use of self.csr.add since to avoid breaking Linux driver that currently relies on implicit ordering (but probably shoudln't :)).
2021-03-25 14:54:34 +01:00
e755a02b84
cpu/vexriscv_smp add RVC support
2021-03-25 14:17:19 +01:00
aad56a047a
integration/soc: Use CSR automatic allocation.
2021-03-25 10:09:54 +01:00
aa9eb1f6a3
integration/soc: Add CSR automatic allocation and enable it by default.
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Un-allocated CSRs were already automatically detected so when un-allocated we can just
simply allocate them automatically instead of raising an error. This also allows
simplifying user's code since self.csr.add/self.add_csr will no longer be required.
2021-03-25 09:49:59 +01:00
3def6ae985
integration/soc: Be sure all add_xy methods use check_if_exists, improve Video integration.
2021-03-25 09:29:33 +01:00
c9ac5424f4
integration/soc: Cosmetic cleanup pass.
2021-03-25 09:13:43 +01:00
6e23fb1d99
integration/soc: Move Identifier import to add_identifier.
2021-03-25 08:47:05 +01:00
e1b20a934a
integation/soc: Move VideoXY imports to add_video_xy.
2021-03-25 08:45:55 +01:00
1b9eefbee4
integration/soc: Move Timer import to add_timer.
2021-03-25 08:43:52 +01:00
01fdca9149
integration/soc: Move SPIMaster import to add_spi_sdcard.
2021-03-25 08:42:23 +01:00
5229727c2b
integration/soc: Move SpiFlash import to add_spi_flash.
2021-03-25 08:40:53 +01:00
c60938d7aa
integration/soc/ethernet: Simplify timing constraints.
2021-03-25 08:36:37 +01:00
e27330b0d9
integration/soc: Replace self.add_csr with self.csr.add.
2021-03-25 08:23:39 +01:00
36bb069b8b
interconnect/packet: Minor cleanup.
2021-03-24 18:04:20 +01:00
6c640b0693
compat/stream_sim: Remove TODO since will not be done.
2021-03-24 17:58:13 +01:00
9eb318e86a
soc/interconnect/stream_sim: Move to compat to prevent since no longer really used or recommended on new designs.
2021-03-24 17:56:21 +01:00
bc8974dad1
litex_sim: Switch to soc_core_args/soc_core_argdict.
2021-03-24 17:26:48 +01:00
ee36138f75
compat: Fix (only triggers notice when used) and enable SoCSDRAM compat.
2021-03-24 17:21:26 +01:00
50ed5e262d
integration/soc_core: Move L2/SDRAM arguments soc_core_args.
2021-03-24 17:21:22 +01:00
ad63f8edc8
compat: Add Retro-Compat for litex.soc.cores.up5kspram (that has now moved to litex.soc.cores.ram).
2021-03-24 17:21:18 +01:00
f7f277548e
Compat: Add litex.compat to handle retro-compatibility on API changes and move integration/soc_sdram to it.
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Compat Notice is not yet enabled for soc_sdram since targets first need to be updated.
2021-03-24 17:21:13 +01:00
cc02055b42
Merge pull request #859 from Dolu1990/master
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soc/cores/cpu/vexriscv_smp cpu per fpu ratio
2021-03-24 08:03:38 +01:00
391a4429dc
soc/cores/cpu/vexriscv_smp add cpu_per_fpu option to change the ratio core count and FPU
2021-03-23 20:05:28 +01:00
9e341544d5
Merge pull request #858 from antmicro/jboc/gtkwave-fix
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gtkwave: fix error when prefix is empty, make treeopen optional
2021-03-23 17:02:23 +01:00
bea82efc5d
gtkwave: fix error when prefix is empty, make treeopen optional
2021-03-23 10:08:06 +01:00
9113c1a2f9
cores/gpio/GPIOIRQ: Add mode CSR (Edge or Change) and rename polarity CSR to edge.
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Allow interrupts on Change, Rising Edge or Falling Edge.
2021-03-20 21:49:12 +01:00
c2f65b2b04
Merge pull request #850 from Dolu1990/master
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cpu/vexriscv_smp add FPU support
2021-03-19 09:08:44 +01:00
db353526c1
Merge pull request #853 from mczerski/liteeth_slots
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liteeth: allow to specify nrxslots and ntxslots for liteeth
2021-03-19 08:58:44 +01:00
d0c4199096
cores/gpio: Fix GPIOIRQ.
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Compilation tested in Arty with:
from litex.soc.cores.gpio import GPIOIn
self.submodules.gpio_in = GPIOIn(platform.request("user_sw", 0), with_irq=True)
self.add_csr("gpio_in")
self.add_interrupt("gpio_in")
2021-03-18 19:05:12 +01:00
1bb4507d93
Merge pull request #846 from enjoy-digital/axi-lite-downconverter-fix
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interconnect/axi: Fix AXILiteDownverterWrite/Read base address.
2021-03-18 18:15:52 +01:00
8460523f27
cores/video: Add VideoECP5HDMI PHY and move 10to1 Serializer to Generic, share it for Spartan6/ECP5.
2021-03-18 14:43:21 +01:00
e5695f9934
cores/video: Add VideoS6HDMIPHY (using stream.Gearbox for 10:2 convertion).
2021-03-18 13:49:50 +01:00
c01284fa23
integration/soc/add_video_colorbars: Review/Fix #849 (Fix ColorBarsPattern clock domain).
2021-03-18 13:48:53 +01:00
675349055b
inteconnect/stream: Increase io_lcm size when io_lcm/i_dw or io_lcm/o_dw < 2.
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Allow supporting all cases.
2021-03-18 13:47:10 +01:00
6eaa426e37
liteeth: allow to specify nrxslots and ntxslots for liteeth
2021-03-18 09:24:48 +01:00
6b387eb579
cpu/vexriscv_smp add FPU support
2021-03-17 13:20:45 +01:00
Geert Uytterhoeven
Florent Kermarrec
Gabriel Somlo
Dolu1990
Jędrzej Boczar
Marek Czerski