7 commits

Author	SHA1	Message	Date
Florent Kermarrec	a99a902fef	add vcd generator	2012-08-26 20:56:56 +02:00
Florent Kermarrec	97cca81e0c	tb_TriggerCsr.py : use truth table generator for Sum Lut	2012-08-26 15:44:43 +02:00
Florent Kermarrec	bf7864104a	tb_spi2Csr: Add clk_ratio ... tb_spi2Csr: Add Read spi2Csr : fixs	2012-08-26 13:03:11 +02:00
Florent Kermarrec	2e54001fc1	- fix Spi2Csr mistakes	2012-08-25 23:29:23 +02:00
Florent Kermarrec	b5a44f2e98	add sim: tb_Spi2Csr.py (skeleton, WIP)	2012-08-25 21:53:06 +02:00
Florent Kermarrec	d14ffb9146	add sim: tb_TriggerCsr.py	2012-08-25 18:46:58 +02:00
Florent Kermarrec	f4cac2c102	Add simulation skeleton ... Remove SRLC16E, will be replaced by distributed ram	2012-08-22 23:59:00 +02:00