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3708 Commits

Author SHA1 Message Date
Sergiusz Bazanski ef6c517dad Build top module as 'dut' in Verilator and set it as top-level. 
When building a design with PicoRV32 we end up with multiple top-level
modules and Verilator becomes confused as to which is the right one.
This change ensures the dut.v generated by the sim build process has
it's top-level name set to 'dut' and that verilator is invoked with this
name.
 2018-01-23 01:15:28 +00:00
enjoy-digital a385143779
Merge pull request #59 from q3k/for-upstream/multiple-synthesis-directives 
Allow for multiple synthesis directives in specials.
 2018-01-23 01:43:23 +01:00
Sergiusz Bazanski 21bd26dcdd Allow for multiple synthesis directives in specials. 
This is needed to specify timing constraints on some Lattice Diamond
library specials, like the EHXPLLL.

To keep backwards compatibility we allow the directive to still be a
single string. If it's not, we assume it's an iterable.
 2018-01-23 00:27:49 +00:00
Florent Kermarrec 67f8718b26 minor cleanup 2018-01-23 00:35:20 +01:00
enjoy-digital d07ddd11d9
Merge pull request #58 from q3k/for-upstream/picorv32-support 
Implement IRQ for PicoRV32 on LiteX
 2018-01-22 22:09:46 +01:00
Sergiusz Bazanski 6daf3eabc5 Implement IRQ software support for RISC-V. 
Well, at least PicoRV32-specific. Turns out there is no RISC-V
specification for simple microcontroller-like interrupts, so PicoRV32
implements its' own based on custom opcodes.

It's somewhat esoteric, and for example doesn't offer a global interrupt
enable/disable. For this we implement a thin wrapper in assembly and
then expose it via a few helpers in irq.h.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski 2108c97b9b Import PicoRV32-specific instruction macros. 
These come from the PicoRV32 repo and are released under the public
domain [1].

[1] - 70f3c33ac8/firmware/custom_ops.S
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski cf74c781f4 Write init files that respect CPU's endianness. 
This is required for PicoRV32 support. We also drive-by enable
explicit specification of run= in Builder.build() by callers.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski 7176492231 Set the MABI and MArch of the riscv target. 
Again, this should be tunable, and synchronized with the core settings.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski 7ea5a26734 Enable hardware multiplier and divider in PicoRV32 
This should become tunable later once we can configure whether we link
in the soft mul library or not.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski 75e230aae7 Replace __riscv__ macros with __riscv. 
The __riscv__ form is deprecated [1].

[1] - https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski 20ed23443b Export trap signal from PicoRV32. 
This is useful for handling crashes from hardware.
 2018-01-22 18:50:26 +00:00
Sergiusz Bazanski b0be563012 Bump PicoRV32 version. 2018-01-22 18:50:26 +00:00
Ewen McNeill 75e7f9505a BIOS: Flashboot without main ram 
Modified flashboot() to skip copy to main ram if there is no main
ram, and instead execute in place out of SPI flash.  (For this to
work the linker .ld will also need to redirect references to be
inside the SPI flash mapping.)
 2018-01-20 15:05:47 +11:00
Florent Kermarrec 3a5f93db5d software/bios: add litex logo 2018-01-19 18:41:13 +01:00
enjoy-digital d6877300c2
Merge pull request #56 from cr1901/mimasv2 
Add mimasv2 platform (pulled from litex-buildenv).
 2018-01-19 17:59:47 +01:00
William D. Jones c553fe2bf3 Add mimasv2 platform (pulled from litex-buildenv). 2018-01-19 06:16:04 -05:00
Tim Ansell d6f2f63794
Merge pull request #53 from mithro/allow-forcing-colorama 
Support forcing colorama colors on.
 2018-01-18 16:33:02 +11:00
Tim 'mithro' Ansell ead88ed66d Support forcing colorama colors on. 
This is needed if you want colors but are using pipes and similar.
 2018-01-18 14:41:45 +11:00
Tim Ansell fcc22350fb
Merge pull request #52 from ewen-naos-nz/tftp-alt-port 
BIOS: Support alternate TFTP server port
 2018-01-18 13:40:28 +11:00
Ewen McNeill 5ce8ca8e9b BIOS: TFTP: try UDP/69 if specified port fails 2018-01-18 13:10:28 +11:00
Ewen McNeill cb31266500 BIOS: set TFTP_SERVER_PORT from enviroment 2018-01-18 13:09:34 +11:00
Ewen McNeill 97f381baa6 BIOS: allow BIOS to specify TFTP server port 
Swaps hard coded PORT_OUT in tftp.c for parameter on the tftp_get()
and tftp_put() functions.  Allow TFTP_SERVER_PORT used by BIOS to be
set at compile time from compiler defines.
 2018-01-18 12:03:35 +11:00
enjoy-digital e06bb3724b
Merge pull request #51 from felixheld/liteeth-untangling 
Include the ethernet related header files conditionally
 2018-01-16 21:37:24 +01:00
Felix Held 21ad435def Include the ethernet related header files conditionally 
Only including those header files in the litex firmware is the first step to
move the firmware parts of liteeth to the liteeth tree.
 2018-01-16 14:33:49 +11:00
Tim Ansell ab1146e1b0
Merge pull request #49 from mithro/fix-uart-override 
soc_core: Don't fail if name is the same.
 2018-01-13 19:12:50 +11:00
Tim 'mithro' Ansell 3d40ad0a82 soc_core: Don't fail if name is the same. 
Otherwise you can't override the UART with another UART, you get an
error like;

```
  File "/home/tansell/github/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/integration/soc_core.py", line 176, in __init__
    interrupt, mod_name, interrupt_rmap[interrupt]))
AssertionError: Interrupt vector conflict for IRQ 2, user defined uart conflicts with SoC inbuilt uart
```
 2018-01-13 19:10:57 +11:00
Tim Ansell bebaef1e25
Merge pull request #48 from mithro/fix-constants 
cpu_interface: Fix indenting on constant generation.
 2018-01-13 19:07:04 +11:00
Tim 'mithro' Ansell f6f73cf13c cpu_interface: Fix indenting on constant generation. 
This was preventing constants from getting added to the csr.h header
file.
 2018-01-13 19:05:26 +11:00
Tim Ansell d37cf226d6
Merge pull request #47 from felixheld/indentation-fixes 
Fix all remaining indentation issues in python code
 2018-01-13 13:29:29 +11:00
Felix Held 6318a2b29a Fix all remaining indentation issues in python code 
I ran a script that shouldn't have missed any tab in the python source files.
 2018-01-13 13:19:36 +11:00
Chris Ballance 782711e5a9 bios/sdram: make read leveling robust for KUS SDRAM 
Increases the initial delay step into the valid read window as
with the original delay I was not getting out of the noisy
transition window, as evidenced by seeing read delay windows
of only 8 LSB ~10% of the time, leading to failing memory
tests
 2018-01-12 19:23:08 +01:00
Tim Ansell 5c95c8ead0
Merge pull request #44 from felixheld/nexys_video-dram-fix 
Fix DDR3 on nexys_video
 2018-01-12 14:08:03 +11:00
Tim Ansell c2c622691c
Merge pull request #45 from felixheld/arty-ddr3-fix 
fix DDR3 on arty
 2018-01-12 14:07:32 +11:00
Felix Held 9eb1beea04 fix DDR3 on arty 2018-01-12 13:54:10 +11:00
Felix Held 4a3454107a fix DDR3 on nexys_video 2018-01-12 13:33:13 +11:00
enjoy-digital 7b6ba372c8
Merge pull request #43 from felixheld/programmer-error-fix 
fix the unsupported programmer case for kc705 and minispartan6
 2018-01-11 08:21:46 +01:00
Felix Held 23585385c0 fix the unsupported programmer case for kc705 and minispartan6 2018-01-11 18:15:11 +11:00
Tim Ansell b2beec267b
Merge pull request #42 from felixheld/requirements-fix 
add pyserial to the package requirements
 2018-01-11 17:46:21 +11:00
Felix Held 99cf4d9f26 add pyserial to the package requirements 
litex_term requires pyserial
 2018-01-11 17:43:16 +11:00
Florent Kermarrec 10000eb607 build/xilinx/vivado: only generate constraints that are not empty 2018-01-08 17:03:19 +01:00
Florent Kermarrec 5681a3c1a9 bios/sdram: revert capability to do manual read leveling since still needed with some targets 2018-01-08 12:04:33 +01:00
Florent Kermarrec 03eb137449 bios/sdram: fix data error reporting 2018-01-08 11:43:49 +01:00
Florent Kermarrec 22ff745027 bump year 2018-01-08 11:43:13 +01:00
Florent Kermarrec ee6b33e9d3 build: add Inverted property to IOs to ease inverting signals and propagate property to cores 2018-01-06 01:33:02 +01:00
Florent Kermarrec 621aaf6988 soc/integration/soc_core: avoid removing uart interrupts (break some designs) 2017-12-30 18:41:49 +01:00
enjoy-digital 377af99678
Merge pull request #40 from mithro/or1k-linux 
cpu: Adding "variant" support.
 2017-12-30 11:19:12 +01:00
enjoy-digital f8a07c5d3c
Merge pull request #41 from cr1901/python-3.6 
fhdl/tracer: Import Python 3.5/3.6 version guards from Migen.
 2017-12-30 11:17:41 +01:00
William D. Jones ff0ad9a622 fhdl/tracer: Import Python 3.5/3.6 version guards from Migen. 2017-12-29 19:56:52 -05:00
Tim 'mithro' Ansell 44650dffd8 cpu: Adding "variant" support. 
It is useful to support slightly different variants of the CPU
configurations. This adds a "cpu_variant" option.

For the mor1k we now have the default mor1k configuration and the
"linux" variant which enables the features needed for Linux support on
the mor1k.

Currently there are no variants for the lm32, but we will likely add a
"tiny" variant for usage on the iCE40.
 2017-12-30 01:18:51 +01:00