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7 commits

Author SHA1 Message Date
Florent Kermarrec
3978af9c39 test/test_hyperbus: Update. 2024-04-16 11:12:30 +02:00
Florent Kermarrec
6216bd4e99 cores/hyperbus: Add latency_mode parameter and test different latencies/modes in simulation. 2024-04-15 10:32:13 +02:00
Florent Kermarrec
b192103822 cores/hyperbus: Fix bytes order on register writes. 2024-04-12 16:06:26 +02:00
Florent Kermarrec
fb519ac260 test/test_hyperbus: Add test_hyperram_reg_write. 2024-04-12 15:21:57 +02:00
Florent Kermarrec
dbde036162 soc/cores: Re-integrated generic/portable HyperBus/HyperRAM core from LiteHyperBus. 
The generic version of the HyperRAM core is simple enough to be directly integrated in LiteX
which avoid an additional dependency.
 2022-03-01 09:11:55 +01:00
Florent Kermarrec
6f8f0d2346 litex_setup: add litehyperbus and remove hyperbus core/test. 2020-05-19 15:49:25 +02:00
Florent Kermarrec
4990bf33c0 soc/core: simplify/cleanup HyperRAM core 
- rename core to hyperbus.
- change layout (cs_n with variable length instead of cs0_n, cs1_n).
- use DifferentialOutput when differential clock is used.
- add test (python3 -m unittest test.test_hyperbus).

Usage example:
from litex.soc.cores.hyperbus import HyperRAM
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
 2019-08-16 14:04:58 +02:00