Sebastien Bourdeauducq
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17b2588321
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ddrphy: reads OK, write data coming out 1/2 cycle too late
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2012-02-24 15:05:52 +01:00 |
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Sebastien Bourdeauducq
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a363eb4a36
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ddrphy: partly working
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2012-02-24 13:54:10 +01:00 |
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Sebastien Bourdeauducq
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92ac69bae3
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dfii: new design
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2012-02-23 21:21:07 +01:00 |
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Sebastien Bourdeauducq
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f35cd4a85b
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Prepare for new DDR PHY
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2012-02-19 18:43:42 +01:00 |
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Sebastien Bourdeauducq
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1e4e092a55
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bios: fix function prototypes
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2012-02-18 21:06:35 +01:00 |
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Sebastien Bourdeauducq
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026457a98c
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Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately.
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2012-02-18 18:12:14 +01:00 |
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Sebastien Bourdeauducq
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c38de34a21
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bios: DDR initialization skeleton
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2012-02-17 18:47:04 +01:00 |
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Sebastien Bourdeauducq
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e5927e265f
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bios: add flash target using m1nor
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2012-02-17 18:16:29 +01:00 |
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Sebastien Bourdeauducq
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73fce59631
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software: shell from original BIOS
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2012-02-07 15:02:44 +01:00 |
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Sebastien Bourdeauducq
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ef0667d959
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software: UART RX demo
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2012-02-07 14:12:33 +01:00 |
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Sebastien Bourdeauducq
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fb22edc06a
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software: enable -Wmissing-prototypes
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2012-02-07 13:02:06 +01:00 |
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Sebastien Bourdeauducq
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4aaf48afb0
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software: interrupt driven UART working
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2012-02-06 23:53:29 +01:00 |
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Sebastien Bourdeauducq
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5cde57cb65
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software: use new UART
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2012-02-06 17:53:41 +01:00 |
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Sebastien Bourdeauducq
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45529d5941
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BIOS: hello world
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2012-02-05 20:01:28 +01:00 |