c14502807e
board/targets/nexys4ddr: use MT47H64M16
2018-02-06 19:17:54 +01:00
95ebba428c
boards/platforms/nexys4ddr: add user_sw, user_btn, fix ddr3
2018-02-06 19:08:46 +01:00
ee4fa597b4
boards: add nexys4ddr
2018-02-06 14:43:20 +01:00
2ecd1b0666
Merge pull request #61 from PaulSchulz/master
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platform/arty.py: Move Pmod definitions to 'connectors' section.
2018-01-26 01:58:37 +01:00
c83ae98be3
Merge pull request #63 from cr1901/arty_s7
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boards/platforms: Add Arty S7 Board.
2018-01-26 01:57:50 +01:00
4607e5323f
boards/platforms: Add Arty S7 Board.
2018-01-25 18:36:32 -05:00
0ac35300c4
Merge branch 'master' of https://github.com/enjoy-digital/litex into upstream
2018-01-24 13:32:42 +10:30
4f2725809e
software/common: revert PYTHON to python3 (since breaking things)
2018-01-23 10:39:13 +01:00
4e168221d8
bios: fix riscv processor print
2018-01-23 10:33:05 +01:00
d448874879
sim: rename top module to dut and use --top-module parameter (needed for picorv32 simulation)
2018-01-23 10:28:16 +01:00
3ac28ed6f7
platform/arty.py: Move Pmod definitions to 'connectors' section.
2018-01-23 16:11:25 +10:30
a385143779
Merge pull request #59 from q3k/for-upstream/multiple-synthesis-directives
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Allow for multiple synthesis directives in specials.
2018-01-23 01:43:23 +01:00
21bd26dcdd
Allow for multiple synthesis directives in specials.
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This is needed to specify timing constraints on some Lattice Diamond
library specials, like the EHXPLLL.
To keep backwards compatibility we allow the directive to still be a
single string. If it's not, we assume it's an iterable.
2018-01-23 00:27:49 +00:00
67f8718b26
minor cleanup
2018-01-23 00:35:20 +01:00
d07ddd11d9
Merge pull request #58 from q3k/for-upstream/picorv32-support
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Implement IRQ for PicoRV32 on LiteX
2018-01-22 22:09:46 +01:00
6daf3eabc5
Implement IRQ software support for RISC-V.
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Well, at least PicoRV32-specific. Turns out there is no RISC-V
specification for simple microcontroller-like interrupts, so PicoRV32
implements its' own based on custom opcodes.
It's somewhat esoteric, and for example doesn't offer a global interrupt
enable/disable. For this we implement a thin wrapper in assembly and
then expose it via a few helpers in irq.h.
2018-01-22 18:50:26 +00:00
2108c97b9b
Import PicoRV32-specific instruction macros.
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These come from the PicoRV32 repo and are released under the public
domain [1].
[1] - 70f3c33ac8/firmware/custom_ops.S
2018-01-22 18:50:26 +00:00
cf74c781f4
Write init files that respect CPU's endianness.
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This is required for PicoRV32 support. We also drive-by enable
explicit specification of run= in Builder.build() by callers.
2018-01-22 18:50:26 +00:00
7176492231
Set the MABI and MArch of the riscv target.
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Again, this should be tunable, and synchronized with the core settings.
2018-01-22 18:50:26 +00:00
7ea5a26734
Enable hardware multiplier and divider in PicoRV32
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This should become tunable later once we can configure whether we link
in the soft mul library or not.
2018-01-22 18:50:26 +00:00
75e230aae7
Replace __riscv__ macros with __riscv.
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The __riscv__ form is deprecated [1].
[1] - https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions
2018-01-22 18:50:26 +00:00
20ed23443b
Export trap signal from PicoRV32.
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This is useful for handling crashes from hardware.
2018-01-22 18:50:26 +00:00
b0be563012
Bump PicoRV32 version.
2018-01-22 18:50:26 +00:00
3a5f93db5d
software/bios: add litex logo
2018-01-19 18:41:13 +01:00
d6877300c2
Merge pull request #56 from cr1901/mimasv2
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Add mimasv2 platform (pulled from litex-buildenv).
2018-01-19 17:59:47 +01:00
c553fe2bf3
Add mimasv2 platform (pulled from litex-buildenv).
2018-01-19 06:16:04 -05:00
d6f2f63794
Merge pull request #53 from mithro/allow-forcing-colorama
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Support forcing colorama colors on.
2018-01-18 16:33:02 +11:00
ead88ed66d
Support forcing colorama colors on.
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This is needed if you want colors but are using pipes and similar.
2018-01-18 14:41:45 +11:00
fcc22350fb
Merge pull request #52 from ewen-naos-nz/tftp-alt-port
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BIOS: Support alternate TFTP server port
2018-01-18 13:40:28 +11:00
5ce8ca8e9b
BIOS: TFTP: try UDP/69 if specified port fails
2018-01-18 13:10:28 +11:00
cb31266500
BIOS: set TFTP_SERVER_PORT from enviroment
2018-01-18 13:09:34 +11:00
97f381baa6
BIOS: allow BIOS to specify TFTP server port
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Swaps hard coded PORT_OUT in tftp.c for parameter on the tftp_get()
and tftp_put() functions. Allow TFTP_SERVER_PORT used by BIOS to be
set at compile time from compiler defines.
2018-01-18 12:03:35 +11:00
e06bb3724b
Merge pull request #51 from felixheld/liteeth-untangling
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Include the ethernet related header files conditionally
2018-01-16 21:37:24 +01:00
21ad435def
Include the ethernet related header files conditionally
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Only including those header files in the litex firmware is the first step to
move the firmware parts of liteeth to the liteeth tree.
2018-01-16 14:33:49 +11:00
ab1146e1b0
Merge pull request #49 from mithro/fix-uart-override
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soc_core: Don't fail if name is the same.
2018-01-13 19:12:50 +11:00
3d40ad0a82
soc_core: Don't fail if name is the same.
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Otherwise you can't override the UART with another UART, you get an
error like;
```
File "/home/tansell/github/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/integration/soc_core.py", line 176, in __init__
interrupt, mod_name, interrupt_rmap[interrupt]))
AssertionError: Interrupt vector conflict for IRQ 2, user defined uart conflicts with SoC inbuilt uart
```
2018-01-13 19:10:57 +11:00
bebaef1e25
Merge pull request #48 from mithro/fix-constants
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cpu_interface: Fix indenting on constant generation.
2018-01-13 19:07:04 +11:00
f6f73cf13c
cpu_interface: Fix indenting on constant generation.
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This was preventing constants from getting added to the csr.h header
file.
2018-01-13 19:05:26 +11:00
d37cf226d6
Merge pull request #47 from felixheld/indentation-fixes
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Fix all remaining indentation issues in python code
2018-01-13 13:29:29 +11:00
6318a2b29a
Fix all remaining indentation issues in python code
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I ran a script that shouldn't have missed any tab in the python source files.
2018-01-13 13:19:36 +11:00
782711e5a9
bios/sdram: make read leveling robust for KUS SDRAM
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Increases the initial delay step into the valid read window as
with the original delay I was not getting out of the noisy
transition window, as evidenced by seeing read delay windows
of only 8 LSB ~10% of the time, leading to failing memory
tests
2018-01-12 19:23:08 +01:00
5c95c8ead0
Merge pull request #44 from felixheld/nexys_video-dram-fix
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Fix DDR3 on nexys_video
2018-01-12 14:08:03 +11:00
c2c622691c
Merge pull request #45 from felixheld/arty-ddr3-fix
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fix DDR3 on arty
2018-01-12 14:07:32 +11:00
9eb1beea04
fix DDR3 on arty
2018-01-12 13:54:10 +11:00
4a3454107a
fix DDR3 on nexys_video
2018-01-12 13:33:13 +11:00
7b6ba372c8
Merge pull request #43 from felixheld/programmer-error-fix
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fix the unsupported programmer case for kc705 and minispartan6
2018-01-11 08:21:46 +01:00
23585385c0
fix the unsupported programmer case for kc705 and minispartan6
2018-01-11 18:15:11 +11:00
b2beec267b
Merge pull request #42 from felixheld/requirements-fix
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add pyserial to the package requirements
2018-01-11 17:46:21 +11:00
99cf4d9f26
add pyserial to the package requirements
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litex_term requires pyserial
2018-01-11 17:43:16 +11:00
10000eb607
build/xilinx/vivado: only generate constraints that are not empty
2018-01-08 17:03:19 +01:00
Florent Kermarrec
William D. Jones
Paul Schulz
Sergiusz Bazanski
Tim Ansell
Ewen McNeill
Felix Held
Chris Ballance