Sebastien Bourdeauducq
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c86dd3cbef
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Define clock domains instead of passing extra clocks as regular signals
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2012-09-11 00:21:07 +02:00 |
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Sebastien Bourdeauducq
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6776e2275c
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Work around imbecilic timing constraints system
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2012-07-01 18:14:16 +02:00 |
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Sebastien Bourdeauducq
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3a02524cc7
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VGA framebuffer connections
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2012-06-17 13:41:26 +02:00 |
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Sebastien Bourdeauducq
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4e18e45686
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Add Ethernet MAC
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2012-05-20 00:30:03 +02:00 |
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Sebastien Bourdeauducq
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19b1cc2529
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Remove uses of pads, new constraints system
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2012-04-02 19:22:17 +02:00 |
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Sebastien Bourdeauducq
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4c1e18a9b5
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s6ddrphy: clock, address and command
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2012-02-19 20:49:56 +01:00 |
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Sebastien Bourdeauducq
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f35cd4a85b
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Prepare for new DDR PHY
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2012-02-19 18:43:42 +01:00 |
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Sebastien Bourdeauducq
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5d1dad583b
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Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
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2012-02-17 11:04:44 +01:00 |
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Sebastien Bourdeauducq
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72f9af9d90
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Generate all clocks for the DDR PHY
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2012-02-16 18:02:37 +01:00 |
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Sebastien Bourdeauducq
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0e30d67fa3
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Multiply system clock
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2011-12-17 15:00:18 +01:00 |
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Sebastien Bourdeauducq
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411e1af980
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Proper reset generation
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2011-12-16 22:25:26 +01:00 |
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Sebastien Bourdeauducq
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ca68097ef6
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Pay a bit more attention to PEP8
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2011-12-16 16:02:49 +01:00 |
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Sebastien Bourdeauducq
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b487e99bcf
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Initial import
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2011-12-13 17:33:12 +01:00 |