Florent Kermarrec
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1b58813d13
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soc: do_exit is now provided by modules
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2015-03-09 17:18:42 +01:00 |
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Florent Kermarrec
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af66ca7bad
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uart: add phy autodetect function
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2015-03-06 10:19:29 +01:00 |
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Florent Kermarrec
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bee8ccf6c7
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soc: enforce cpu_reset_address to 0 when with_rom is True
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2015-03-06 08:21:16 +01:00 |
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Florent Kermarrec
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0bcd6daf63
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soc: remove is_sim function
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2015-03-03 10:15:11 +01:00 |
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Florent Kermarrec
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f58394f6af
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soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)
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2015-03-01 18:25:47 +01:00 |
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Florent Kermarrec
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bd4d3cd73b
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uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)
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2015-03-01 12:14:34 +01:00 |
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Florent Kermarrec
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144ee7ea9f
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soc: fix register_rom
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2015-02-28 23:51:51 +01:00 |
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Florent Kermarrec
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5c43d4d091
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litescope: create example design derived from SoC that can be used on all targets
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2015-02-28 22:19:24 +01:00 |
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Florent Kermarrec
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165a5b6760
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soc: use self.cpu_reset_address as rom mem_map address and increase default bios size to 0xa000
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2015-02-28 20:04:51 +01:00 |
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Florent Kermarrec
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8564b7eb6a
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soc: move SDRAMSoC to a separate sdram.py file (ideally part of SDRAMSoC should move mem/sdram)
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2015-02-28 11:44:14 +01:00 |
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Florent Kermarrec
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69e869893d
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remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
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2015-02-28 11:36:15 +01:00 |